Memory systems and memory programming methods

A memory system comprising:

• a memory cell configured to have a plurality of different memory states at a plurality of different moments in time, wherein the memory cell comprises a memory element between a plurality of electrodes, the memory element comprises a dielectric material between the electrodes, and the memory element is configured to have different electrical resistances corresponding to the different memory states of the memory cell;
• program circuitry configured to provide a first program signal to the memory cell to break an electrical connection within the dielectric material which electrically connects the electrodes of the memory cell with one another and the breakage of the electrical connection changes an electrical resistance of the memory cell from a low electrical resistance corresponding to a first of the different memory states to a high electrical resistance corresponding to a second of the different memory states;
• and
• wherein the program circuitry is configured to provide a second program signal to the memory cell having the high electrical resistance to enable the memory cell to retain the high electrical resistance after the provision of the first and second program signals to the memory cell.

A memory system comprising:

• a memory cell configured to have a plurality of different memory states at different moments in time;
• program circuitry configured to provide a plurality of program signals to the memory cell to change the memory cell from a first of the different memory states to a second of the different memory states;
• and
• wherein the provision of a first of the program signals to the memory cell changes the memory cell from the first memory state to the second memory state and the provision of a second of the program signals to the memory cell enables the memory cell to retain the second memory state after the provision of the first and second program signals to the memory cell.

A memory system comprising:

• a memory cell configured to have a plurality of different memory states at different moments in time;
• a driver transistor configured to generate a plurality of different program signals which are provided to the memory cell to program the memory cell from a first of the different memory states to a second of the different memory states;
• wherein a first bias voltage is applied to a gate of the driver transistor during the provision of a first of the different program signals to the memory cell and a second bias voltage is applied to the gate of the driver transistor during the provision of a second of the different program signals to the memory cell, and wherein the first and second bias voltages are different;
• and
• wherein the first program signal changes the memory cell from the first memory state to the second memory state and the second program signal enables the memory cell to retain the second memory state after the provision of the first and second program signals to the memory cell.

A memory cell programming method comprising:

• using a source follower amplifier, providing a first program signal to a memory cell in a first of a plurality of different memory states;
• as a result of the providing the first program signal to the memory cell, changing the memory cell from the first memory state to a second of the different memory states;
• as a result of the changing the memory cell, changing a load line of the source follower amplifier;
• and
• using the source follower amplifier with the changed load line, providing a second program signal to the memory cell in the second memory state.

A memory system comprising:

• a bit line;
• a memory cell coupled with the bitline, and wherein the memory cell is configured to have a plurality of different memory states at different moments in time;
• a first voltage source configured to provide a first program signal to the bit line and the memory cell at a first moment in time to change the memory cell from a first of the memory states to a second of the memory states;
• a second voltage source configured to provide a second program signal to the bit line and the memory cell at a second moment in time while the memory cell is in the second memory state;
• wherein the first and second program signals have different voltages and the first moment in time occurs before the second moment in time;
• and
• wherein the provision of the second program signal enables the memory cell to retain the second memory state after the provision of the first and second program signals to the memory cell.

A memory system comprising:

• a bit line;
• a memory cell coupled with the bitline, and wherein the memory cell is configured to have a plurality of different memory states at different moments in time;
• a first voltage source configured to provide a first program signal to the bit line and the memory cell at a first moment in time to change the memory cell from a first of the memory states to a second of the memory states;
• a second voltage source configured to provide a second program signal to the bit line and the memory cell at a second moment in time while the memory cell is in the second memory state;
• wherein the first and second program signals have different voltages and the first moment in time occurs before the second moment in time;
• wherein the memory cell comprises a memory element which comprises dielectric material between plural electrodes;
• and
• wherein an electrically conductive structure electrically connects the electrodes while the memory cell is in the first memory state and the electrodes are electrically isolated from one another while the memory cell is in the second memory state.

A memory system comprising:

• a memory cell configured to have a plurality of different memory states at different moments in time;
• a driver transistor configured to generate a plurality of different program signals which are provided to the memory cell to program the memory cell from a first of the different memory states to a second of the different memory states;
• wherein a first bias voltage is applied to a gate of the driver transistor during the provision of a first of the different program signals to the memory cell and a second bias voltage is applied to the gate of the driver transistor during the provision of a second of the different program signals to the memory cell, and wherein the first and second bias voltages are different;
• wherein the memory cell comprises a memory element which comprises dielectric material between plural electrodes;
• and
• wherein an electrically conductive structure electrically connects the electrodes while the memory cell is in the first memory state and the electrodes are electrically isolated from one another while the memory cell is in the second memory state.