An electronic device including a semiconductor memory unit, the semiconductor memory unit comprising:
- a cell array including a plurality of storage cells which are connected with first bit lines and first bit line bars or with second bit lines and second bit line bars, and each storage cell stores 1-bit data and includes a first variable resistance element having a first resistance value when a first value is stored therein and a second resistance value when a second value is stored therein and a second variable resistance element having the second resistance value when the first value is stored therein and the first resistance value when the second value is stored therein;
- a first data line and a first data line bar disposed on a first side of the cell array;
- a second data line and a second data line bar disposed on a second side of the cell array;
- one or more first driving blocks disposed on the first side of the cell array and connected to storage cells through the first bit lines and the first bit line bars, each first driving block configured, during a write operation, to latch data of a corresponding first data line and a corresponding first data line bar and drive the corresponding first bit line and the corresponding first bit line bar with a first voltage or a second voltage according to a value of the latched data, and configured, during a read operation, latch data stored in a corresponding storage cell based on current flowing through the corresponding first bit line and the corresponding first bit line bar;
- and
- one or more second driving blocks disposed on the second side of the cell array and connected to storage cells through the second bit lines and the second bit line bars, each second driving block configured, during a write operation, to latch data of a corresponding second data line and a corresponding second data line bar and drive the corresponding second bit line and the corresponding second bit line bar with a first voltage or a second voltage according to a value of the latched data, and configured, during a read operation, to latch data stored in a corresponding storage cell based on current flowing through the corresponding second bit line and the corresponding second bit line bar;
- and
- a plurality of source lines and a plurality of source line bars to which a ground voltage is applied during the read operation,
- wherein each first variable resistance element is connected to a corresponding bit line and a corresponding source line and each second variable resistance element is connected to a corresponding bit line bar and a corresponding source line bar,
- wherein the semiconductor memory unit further comprises:
- a first write connection element connected between the corresponding bit line and a first end of the first driving block, and configured to be turned on in the write operation;
- a second write connection element connected between the corresponding source line bar and the first end of the first driving block, and configured to be turned on in the write operation;
- a third write connection element connected between the corresponding bit line bar and a second end of the first driving block, and configured to be turned on in the write operation;
- and
- a fourth write connection element connected between the corresponding source line and the second end of the first driving block, and configured to be turned on in the write operation;
- a second end of the first driving block, and configured to be turned on in the write operation;
- and
- a fourth write connection element connected between the corresponding source line among the plurality of source lines and the second end of the first driving block, and configured to be turned on in the write operation.