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AssigneeInstitute of Automation, Chinese Academy of Sciences
InventorsJingqiu Wang, Liang Chen, Li Liu
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The memory cell of static random access memory based on resistance-capacitance reinforcement, which comprises a latch circuit and a bit selection circuit, the latch circuit consists of two PMOS transistors P1 and P2, two NMOS transistors N1 and N2, a first resistance-capacitance network and a second resistance-capacitance network; the bit selection circuit consists of NMOS transistors N5 and N6; the latch circuit forms four storage nodes X1, X1B, X2, X2B, among which a coupling capacitor C is provided between a pair of complementary data storage nodes. Compared to the conventional memory cell of 6T structure, a resistance-capacitance network and a coupling capacitor are added, so that without changing the original read operation circuit and without obviously increasing complexity, the memory cell is prevented from having single event upset merely at a cost of increasing a small amount of area, thus ensuring correctness of data.
A memory cell of static random access memory based on resistance-capacitance reinforcement comprising a latch circuit and a bit selection circuit, characterized in that the latch circuit consists of two PMOS transistors P1 and P2, two NMOS transistors N1 and N2, a first resistance-capacitance network and a second resistance-capacitance network;
Dependencies are inferred from the claim text.