Techniques for data retention in memory cells during power interruption

A Static Random Access Memory (SRAM) device, comprising one or more SRAM cells, each SRAM cell comprising:

• a first CMOS inverter, having a first input and a first output;
• a second CMOS inverter, cross-coupled to the first CMOS inverter, and having a second input and a second output;
• a first PMOS transistor, having a first source, a first gate, and a first drain;
• a second PMOS transistor, having a second source, a second gate, and a second drain;
• an electrical capacitive element, comprising a first conductor and a second conductor;
• a first connector, electrically connecting:
• the first output,
• the first drain,
• the second gate, and
• the second input;
• a second connector, electrically connecting:
• the second output,
• the second drain,
• the first gate, and
• the first input;
• and
• a third connector, electrically connecting:
• the first source,
• the second source, and
• the first conductor.

Apparatus comprising a volatile memory device comprising one or more memory circuits, each memory circuit comprising:

• a first CMOS inverter, having a first input and a first output;
• a second CMOS inverter, cross-coupled to the first CMOS inverter, and having a second input and a second output;
• a first PMOS transistor, having a first source, a first gate, and a first drain;
• a second PMOS transistor, having a second source electrically connected to the first source, a second gate, and a second drain;
• a first connector, electrically connecting:
• the first output,
• the first drain,
• the second gate, and
• the second input;
• and
• a second connector, electrically connecting:
• the second output,
• the second drain,
• the first gate, and
• the first input,
• wherein each memory circuit further comprises a third connector, electrically connecting the first source and the second source, wherein each memory circuit further comprises an electrical capacitive element that comprises a first conductor and a second conductor, and wherein the third connector electrically connects the first source, the second source, and the first conductor.

Apparatus comprising a volatile memory device comprising one or more memory circuits, each memory circuit comprising:

• a first CMOS inverter, having a first input and a first output;
• a second CMOS inverter, cross-coupled to the first CMOS inverter, and having a second input and a second output;
• a first PMOS transistor, having a first source, a first gate, and a first drain;
• a second PMOS transistor, having a second source electrically connected to the first source, a second gate, and a second drain;
• a first connector, electrically connecting:
• the first output,
• the first drain,
• the second gate, and
• the second input;
• and
• a second connector, electrically connecting:
• the second output,
• the second drain,
• the first gate, and
• the first input,
• wherein each memory circuit further comprises a third connector, electrically connecting the first source and the second source, and wherein the apparatus further comprises a dielectric in electrical contact with the third connector.

Apparatus comprising a volatile memory device comprising one or more memory circuits, each memory circuit comprising:

• a first CMOS inverter, having a first input and a first output;
• a second CMOS inverter, cross-coupled to the first CMOS inverter, and having a second input and a second output;
• a first PMOS transistor, having a first source, a first gate, and a first drain;
• a second PMOS transistor, having a second source electrically connected to the first source, a second gate, and a second drain;
• a first connector, electrically connecting:
• the first output,
• the first drain,
• the second gate, and
• the second input;
• and
• a second connector, electrically connecting:
• the second output,
• the second drain,
• the first gate, and
• the first input,
• wherein:
• the one or more memory circuits comprises at least a first memory circuit and a second memory circuit,
• the apparatus further comprises a third connector, electrically connecting:
• the first source of the first memory circuit,
• the second source of the first memory circuit,
• the first source of the second memory circuit, and
• the second source of the second memory circuit,
• the apparatus further comprises an electrical capacitive element that comprises a distinct capacitor that comprises a first conductor and a second conductor,
• the third connector electrically connects:
• the first conductor,
• the first source of the first memory circuit,
• the second source of the first memory circuit,
• the first source of the second memory circuit, and
• the second source of the second memory circuit, and
• the electrical capacitive element comprises a distinct capacitor.

Apparatus comprising a volatile memory device comprising one or more memory circuits, each memory circuit comprising:

• a first CMOS inverter, having a first input and a first output;
• a second CMOS inverter, cross-coupled to the first CMOS inverter, and having a second input and a second output;
• a first PMOS transistor, having a first source, a first gate, and a first drain;
• a second PMOS transistor, having a second source electrically connected to the first source, a second gate, and a second drain;
• a first connector, electrically connecting:
• the first output,
• the first drain,
• the second gate, and
• the second input;
• and
• a second connector, electrically connecting:
• the second output,
• the second drain,
• the first gate, and
• the first input,
• wherein:
• the one or more memory circuits comprises at least a first memory circuit and a second memory circuit, and wherein the apparatus further comprises a third connector, electrically connecting:
• the first source of the first memory circuit,
• the second source of the first memory circuit,
• the first source of the second memory circuit, and
• the second source of the second memory circuit, and
• the apparatus further comprises a dielectric in electrical contact with the third connector.