Apparatus, method and system for providing termination for multiple chips of an integrated circuit package

A system comprising:

• a memory controller;
• an interconnect coupled to receive command and address signals from the memory controller;
• and
• an integrated circuit (IC) package coupled to receive the command and address signals from the interconnect, the IC package including:
• a command and address bus;
• a plurality of stacked memory chips each coupled to the command and address bus, each of the plurality of stacked memory chips including a respective on-die termination control circuit of a plurality of on-die termination control circuits coupled to the command and address bus, wherein a first memory chip of the plurality of stacked memory chips includes a first on-die termination control circuit of the plurality of on-die termination control circuits, wherein, for each of the plurality of on-die termination control circuits:
• a respective first termination state of the on-die termination control circuit is to provide termination with the on-die termination control circuit;
• and
• a respective second termination state of the on-die termination control circuit is to prevent any termination from being provided with the on-die termination control circuit;
• wherein, only the first on-die termination control circuit is to selectively provide termination to the command and address bus, wherein, of the plurality of on-die termination circuits:
• the first on-die termination control circuit is farthest away from the inputs/outputs (I/Os) of the IC package than the remaining other on-die termination control circuits of the memory chips other than the first memory chip;
• and
• only the first on-die termination control circuit is coupled to enable an ability to selectively transition, responsive to a termination control signal, between the respective first termination state and the respective second termination state;
• and,
• the remaining other on die termination control circuits of the memory chips other than the first memory chip are to be in a deterministic termination state that is not responsive to the termination control signal and does not terminate the command and address bus.