US 10,121,523 B2Granted

Memory bank signal coupling buffer and method

AssigneeMicron Technology, Inc.

InventorsAidan Shori, Sumit Chopra

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Abstract

A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

Claims19

Dependent claims

An apparatus comprising:

a plurality of data lines configured to transfer respective signals within a plurality of memory cells, a data line of the plurality of data lines being divided into two data line segments;
and
a bidirectional buffer interposed between the two data line segments;
wherein the bidirectional buffer comprises a first transistor coupled to a first of the two data line segments, a second transistor coupled to the first of the two data line segments, a third transistor coupled to a second of the two data line segments, and a fourth transistor coupled to the second of the two data line segments, wherein a source of the first transistor and a source of the third transistor are coupled to a fifth transistor;
and
wherein the bidirectional buffer is configured in a precharge mode to decouple the two data line segments from each other by disabling each of the first, second, third and fourth transistors;
wherein the bidirectional buffer is further configured in an operation mode to couple the first of the two data line segments to the second of the two data line segments by enabling the first transistor and enabling the fourth transistor via enabling at least the fifth transistor, and to couple the second of the two data line segments to the first of the two data line segments by enabling the third transistor and enabling the second transistor via at least the enabled fifth transistor;
wherein the bidirectional buffer further comprises a sixth transistor coupled to the first of the two data line segments and a seventh transistor coupled to the second of the two data line segments;
wherein the bidirectional buffer is further configured in the precharge mode to precharge each of the first and second of the two data line segments by enabling each of the sixth and seventh transistors and in the operation mode to disable each of the sixth and seventh transistors;
wherein the bidirectional buffer further comprises an eighth transistor coupled to the second transistor and a ninth transistor coupled to the fourth transistor;
wherein each of the first and third transistors is disabled in the precharge mode by enabling the sixth and seventh transistors;
and
wherein each of the second and fourth transistors is disabled in the precharge mode by enabling the eighth and ninth transistors.

10 more elements

An apparatus comprising:

a first data line segment;
a second data line segment;
a precharge circuit configured to be activated in a precharge mode to precharge each of the first and second data line segments, wherein the precharge circuit comprises sixth and seventh transistors, wherein the sixth transistor is coupled to the first data line segment, and wherein the seventh transistor is coupled to the second data line segment, wherein the precharge circuit is further configured in the precharge mode to precharge each of the first and the second data line segments by enabling each of the sixth and seventh transistors and in an operation mode to disable each of the sixth and seventh transistors;
a buffer circuit comprising a first transistor coupled to the first data line segment, a second transistor coupled to the first data line segment, a third transistor coupled to the second data line segment and a fourth transistor coupled to the second data line segment, wherein a source of the first transistor and a source of the third transistor are coupled to a fifth transistor;
wherein the buffer circuit is configured to be activated in the operation mode to transfer a first data signal from the first data line segment to the second data line segment by enabling the first transistor and enabling the fourth transistor via enabling at least the fifth transistor and to transfer a second data signal from the second data line segment to the first data line segment by enabling the third transistor and enabling the second transistor via at least the enabled fifth transistor;
wherein the buffer circuit further comprises an eighth transistor coupled to the second transistor and a ninth transistor coupled to the fourth transistor;
wherein each of the first and third transistors is disabled in the precharge mode by enabling the sixth and seventh transistors;
and
wherein each of the second and fourth transistors is disabled in the precharge mode by enabling the eighth and ninth transistors.

6 more elements

An apparatus comprising:

a first memory bank including a plurality of first memory cells;
a second memory bank including a plurality of second memory cells;
a first data line segment elongated over the first memory bank and coupled to the first memory bank;
a second data line segment elongated over the second memory bank and coupled to the second memory bank;
and
a bidirectional buffer inserted between the first and second data line segment;
wherein the bidirectional buffer comprises:
a first transistor including a gate coupled to the first data line segment and a source-drain path coupled to a first node;
a second transistor including a gate coupled to a second node and a drain coupled to the first data line segment;
a third transistor including a gate coupled to the second data line segment and a source-drain path coupled to the second node;
a fourth transistor including a gate coupled to the first node and a drain coupled to the second data line segment;
and
a fifth transistor including a drain coupled to a source of the first transistor and a source of the third transistor;
wherein the bidirectional buffer is configured in a precharge mode to decouple the first and second data line segments from each other by disabling each of the first, second, third and fourth transistors;
and
wherein the bidirectional buffer is further configured in an operation mode to transfer a first data signal from the first data line segment to the second data line segment by enabling the first transistor and enabling the fourth transistor via the enabled fifth transistor, and to transfer a second data signal from the second data line segment to the first data line segment by enabling the third transistor and enabling the second transistor via the enabled fifth transistor;
wherein the bidirectional buffer further comprises a sixth transistor coupled to the first data line segments and a seventh transistor coupled to the second data line segment;
wherein the bidirectional buffer is further configured in the precharge mode to precharge each of the first and second data line segments by enabling each of the sixth and seventh transistors and in the operation mode to disable each of the sixth and seventh transistors;
wherein the bidirectional buffer further comprises an eighth transistor coupled to the second transistor and a ninth transistor coupled to the fourth transistor;
wherein each of the first and third transistors is disabled in the precharge mode by enabling the sixth and seventh transistors;
and
wherein each of the second and fourth transistors is disabled in the precharge mode by enabling the eighth and ninth transistors.

19 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/405,839Filed 13 Jan 2017 · continuation
Priority: 14 Jan 2009
Published: US 2017/0125075 A14 May 2017
Granted: 6 Nov 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 7/10
Arrangements for writing information into, or reading information out from, a digital store: input/output [I/O] data interface arrangements, e.g.…
G11C 7/1048
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data bus control circuits, e.g. precharging,…
G11C 7/22
Arrangements for writing information into, or reading information out from, a digital store: read-write [R-W] timing or clocking circuits;…

Family

Application12/353,661Parent of this continuation · filed 14 Jan 2009
Application13/071,303Parent of this continuation · filed 24 Mar 2011
US 7,929,329 B2Parent of this continuation · filed 19 Apr 2011
Application13/846,452Parent of this continuation · filed 18 Mar 2013
US 8,400,809 B2Parent of this continuation · filed 19 Mar 2013
US 2017/0125075 A1Pre-grant publication · published 4 May 2017
US 9,601,168 B2Parent of this continuation
US 2010/0177571 A1Published application
US 2011/0169534 A1Published application
US 2013/0215699 A1Published application
US 10,121,523 B2This patent

From the US filing history. Foreign family members aren’t listed.

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