US 10,121,522 B1 · Sense circuit with two sense nodes for cascade sensing

Abstract

A sense circuit is provided in which the threshold voltage of a memory cell is sensed relative to two different levels using a single control gate voltage on the memory cell. These two levels can be higher and lower verify voltages of a data state in a programming operation, or two read levels of a read operation. Two sense nodes which are connected in a cascade configuration such that a first sense node discharges into the bit line initially, and a second sense node may or may not discharge into the bit line, depending on the level to which the first node has discharged. First and second bits of data can be output from the sense circuit based on the levels of the first and second sense nodes to indicate the threshold voltage of the memory cell relative to the higher and lower verify voltages, respectively.

Claims20

Dependent claims

An apparatus, comprising:

a first sense node;
a bit line connect transistor between the first sense node and a bit line;
a first trip point transistor connected to the first sense node;
a second sense node;
a second trip point transistor connected to the second sense node;
a separation transistor between first sense node and the second sense node;
and
a control circuit configured to perform a sense operation for a memory cell connected to the bit line, the control circuit configured to:
charge up a voltage of the first sense node to a first level and to charge up a voltage of the second node to a second level;
open the bit line connect transistor in a discharge period;
perform a strobe of an output of the first trip point transistor;
and
perform a strobe of an output of the second trip point transistor.

10 more elements

Dependencies are inferred from the claim text.

Sense circuit with two sense nodes for cascade sensing

Life of this patent

Sense circuit with two sense nodes for cascade sensing

Life of this patent

Abstract

Claims20