Memory array and method of forming the same

A memory array comprising:

• a three-dimensional array comprising:
• a first set of memory cells arranged in a first column;
• and
• a second set of memory cells arranged in a second column;
• the first column comprising:
• a first bit line;
• a first bit line bar;
• and
• a first word line;
• the second column comprising:
• the first bit line bar;
• a second bit line;
• and
• a second word line;
• a first pre-charge circuit coupled to the first bit line;
• a second pre-charge circuit coupled to the first bit line bar;
• and
• a set of switching elements,
• wherein the first column and the second column are configured to share the first bit line bar;
• at least two of the first bit line, the first bit line bar or the second bit line are in a first plane;
• and
• the first word line and the second word line are in a second plane, the second plane intersecting the first plane.

A method comprising:

• forming a first column of memory cells, the first column of memory cells comprising:
• a first bit line;
• a first word line;
• and
• a first bit line bar, the first bit line and the first bit line bar being in a first plane;
• forming a second column of memory cells, the second column of memory cells comprising:
• the first bit line bar;
• a second word line, the first word line and the second word line being in a second plane intersecting the first plane, the first column of memory cells and the second column of memory cells being a three-dimensional array;
• and
• a second bit line;
• sharing the first bit line bar between the first column of memory cells and the second column of memory cells;
• sharing a first pre-charge circuit between the first column of memory cells and the second column of memory cells, the first pre-charge circuit being coupled to at least the first bit line bar;
• and
• providing a word line driver to the first word line and the second word line, the word line driver being below the three-dimensional array.