Driving methods and driving devices of gate driver on array (GOA) circuit

A driving unit of GOA circuits, comprising:

• a timing control chip and a GOA circuit comprising a plurality of cascaded GOA driving units, the timing control chip inputs first clock signals, second clock signals, and a constant-voltage potential to the GOA driving units at each of levels to drive the GOA driving units to output the scanning driving signals level-by-level, wherein scanning initial signals are further inputted to the GOA driving units at the first through the fourth level;
• and
• wherein the first clock signals and the second clock signals are two different clock signals selected from one clock signals set comprising eight high-frequency clock signals (CK1˜CK8), wherein CKm and CKm+4 are inverting signals, and m=1, 2, 3, 4;
• the first clock signals start from the CK5 to output the high-frequency clock signals cyclically, and the second clock signals starts from the CK1 to output the high-frequency clock signals (CK1˜CK8) cyclically, wherein a period of each of the high-frequency clock signals is T, and a high-potential pulse width within the period (T) is T1;
• and
• during a scanning driving process of each of frames, the high-potential pulse width of the high-frequency clock signals (CKm) is T1m, T1m<T1, m=1, 2, 3, and 4.