Display device and gate driving circuit

A display device comprising:

• a display panel comprising a plurality of gate lines;
• and
• a gate driving circuit comprising a plurality of driving stages electrically connected to the gate lines, respectively, a kth driving stage, where k is a natural number of two or more, from among the driving stages comprising:
• an output unit configured to generate a kth output signal based on a clock signal, and to output the kth output signal to an output terminal in response to a voltage of a first node;
• a first control unit configured to control the voltage of the first node;
• a second control unit configured to output a switching signal to a second node, the switching signal being generated based on the clock signal;
• and
• a pull-down unit configured to pull down a voltage of the output terminal after the kth output signal is outputted,
• wherein the first control unit comprises:
• a first control transistor configured to provide an activation signal for activating the output unit to the first node before the kth output signal is outputted;
• and
• second and third control transistors connected in series between the first node and a first voltage input terminal configured to receive a first discharge voltage, and
• wherein the kth output signal is to be directly provided to a first intermediate node between the second control transistor and the third control transistor.

A display device comprising:

• a display panel comprising a plurality of gate lines;
• and
• a gate driving circuit comprising a plurality of driving stages electrically connected to the gate lines, respectively, a kth driving stage, where k is a natural number of two or more, from among the driving stages comprising:
• an output unit configured to generate a kth output signal based on a clock signal, and to output the kth output signal to an output terminal in response to a voltage of a first node;
• a first control unit configured to control the voltage of the first node;
• a second control unit configured to output a switching signal to a second node, the switching signal being generated based on the clock signal;
• and
• a pull-down unit configured to pull down a voltage of the output terminal after the kth output signal is outputted, wherein the pull-down unit comprises:
• a first pull-down unit configured to pull down the first output terminal after the kth gate signal is outputted;
• and
• a second pull-down unit configured to pull down the second output terminal after the kth carry signal is outputted;
• wherein the first control unit comprises:
• a first control transistor configured to provide an activation signal for activating the output unit to the first node before the kth output signal is outputted;
• and
• second and third control transistors connected in series between the first node and a first voltage input terminal configured to receive a first discharge voltage,
• wherein the kth output signal is to be provided to a first intermediate node between the second control transistor and the third control transistor,
• wherein the kth output signal comprises a kth gate signal and a kth carry signal, and the output terminal comprises a first output terminal and a second output terminal, and
• wherein the output unit comprises:
• a first output transistor comprising a control electrode connected to the first node, an input electrode configured to receive the clock signal, and an output electrode configured to output the kth gate signal to the first output terminal;
• a second output transistor comprising a control electrode connected to the first node, an input electrode configured to receive the clock signal, and an output electrode configured to output the kth carry signal to the second output terminal;
• and
• a capacitor connected between the output electrode of the first output transistor and the control electrode of the first output transistor, and
• wherein,
• the first pull-down unit comprises first and second pull-down transistors connected in series between the first output terminal and a second voltage input terminal configured to receive a second discharge voltage having a different level than that of the first discharge voltage, and
• the kth output signal is to be provided to a second intermediate node between the first pull-down transistor and the second pull-down transistor.