Shift register and method for driving the same, gate driving circuit and display device

A shift register, comprising:

• an input module, which comprises a first transistor and a fifth transistor, a first electrode of the first transistor being connected to a power supply voltage terminal, a second electrode of the first transistor being connected to a pulling-up node, a control electrode of the first transistor being connected to a signal input terminal, a first electrode of the fifth transistor being connected to the signal input terminal, a second electrode of the fifth transistor being connected to the pulling-up node, and a control electrode of the fifth transistor being connected to a second clock signal input terminal;
• an output pulling-up module, which comprises a third transistor and a first storage capacitor, a first electrode of the third transistor being connected to a first clock signal input terminal, a second electrode of the third transistor being connected to a signal output terminal, a control electrode of the third transistor being connected to the pulling-up node, a first end of the first storage capacitor being connected to the pulling-up node, and a second end of the first storage capacitor being connected to the signal output terminal;
• a reset-and-noise-reducing module, which comprises a second transistor, a fourth transistor and a second storage capacitor, a first electrode of the second transistor being connected to the pulling-up node, a second electrode of the second transistor being connected to a low voltage terminal, a control electrode of the second transistor being connected to a reset signal input terminal, a first electrode of the fourth transistor being connected to the signal output terminal, a second electrode of the fourth transistor being connected to the low voltage terminal, a control electrode of the fourth transistor being connected to a pulling-down node, a first end of the second storage capacitor being connected to the second clock signal input terminal, and a second end of the second storage capacitor being connected to the control electrode of the fourth transistor;
• and
• a pulling-down module, which comprises a sixth transistor having a first electrode connected to the pulling-down node, a second electrode connected to the low voltage terminal, and a control electrode connected to the pulling-up node, wherein;
• the reset-and-noise-reducing module is configured to turn on the fourth transistor by means of a bootstrapping of the second storage capacitor in a case where a reset signal inputted from the reset signal input terminal and a second clock signal inputted from the second clock signal input terminal are both at a first level, such that the signal output terminal is discharged to a second level via only the fourth transistor, the second level being different from the first level.