Shift register, a gate driving circuit, a display panel and a display apparatus

A shift register, comprising:

• an inputting module, having an input terminal connected to a first reference signal terminal, a control terminal connected to a signal inputting terminal and an output terminal connected to a first node, wherein the inputting module is configured to pull up a potential of the first node under the control of the signal inputting terminal;
• a resetting module, having an input terminal connected to a second reference signal terminal, a control terminal connected to a resetting signal terminal, and an output terminal connected to the first node, wherein the resetting module is configured to pull down the potential of the first node under the control of the resetting signal terminal;
• a pulling up module, having an input terminal and a control terminal connected to a first clock signal terminal, and an output terminal connected to a second node, wherein the pulling up module is configured to pull up the potential of the second node under the control of the first clock signal terminal;
• a pulling down module for the first node, having an input terminal connected to a low level signal terminal, a control terminal connected to the second node, and an output terminal connected to the first node, wherein the pulling down module for the first node is configured to pull down the potential of the first node under the control of the second node;
• a pulling down module for the second node, having an input terminal connected to a low level signal terminal, a first control terminal connected to the first node, a second control terminal connected to a scanning signal outputting terminal, and an output terminal connected to the second node, wherein the pulling down module for the second node is configured to pull down the potential of the second node under the control of the first node and the scanning signal outputting terminal;
• an output controlling module, connected to the low level signal terminal, a second clock signal terminal, the first node, the second node, a third node and the scanning signal outputting terminal, wherein the output controlling module is configured to control the scanning signal outputting terminal to output a signal from the second clock signal terminal, under the control of the first node, and to connect the low level signal terminal with the third node under the control of the second node;
• and
• an output noise reducing module, having an input terminal connected to the third node, a control terminal connected to a high level signal terminal, and an output terminal connected to the scanning signal outputting terminal, wherein the output noise reducing module is configured to perform a noise reduction on a signal from the third node and output a noise reduced signal to the scanning signal outputting terminal.