US 10,121,435 B2Granted

Driver circuit, display device, and electronic device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorAtsushi Umezaki

Life of this patent

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Abstract

To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

Claims34

Dependent claims

A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;
wherein one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises a channel formation region that comprises an oxide semiconductor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the one of the source and the drain of the fifth transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the fourth transistor,
wherein a gate of the second transistor is electrically connected to a gate of the fifth transistor,
wherein a gate of the third transistor is electrically connected to a gate of the sixth transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring capable of supplying a first signal,
wherein a potential of the gate of the second transistor is changed depending on a potential of a second wiring capable of supplying a second signal, and
wherein the second wiring is not electrically connected to the first wiring.

11 more elements

A semiconductor device comprising:

a pixel;
a driver circuit electrically connected to the pixel,
wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;
wherein one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises a channel formation region that comprises an oxide semiconductor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the one of the source and the drain of the fifth transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the fourth transistor,
wherein a gate of the second transistor is electrically connected to a gate of the fifth transistor,
wherein a gate of the third transistor is electrically connected to a gate of the sixth transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring capable of supplying a first signal,
wherein a potential of the gate of the second transistor is changed depending on a potential of a second wiring capable of supplying a second signal, and
wherein the second wiring is not electrically connected to the first wiring.

13 more elements

A semiconductor device comprising:

a driver circuit,
wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor,
wherein one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor comprises a channel formation region that comprises an oxide semiconductor,
wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is directly connected to one of a source and a drain of the third transistor,
wherein one of a source and a drain of the fourth transistor is directly connected to one of a source and a drain of the fifth transistor,
wherein one of a source and a drain of the sixth transistor is directly connected to the one of the source and the drain of the fifth transistor,
wherein the other of the source and the drain of the fourth transistor is directly connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the first transistor is directly connected to the one of the source and the drain of the fourth transistor,
wherein a gate of the second transistor is directly connected to a gate of the fifth transistor,
wherein a gate of the third transistor is directly connected to a gate of the sixth transistor,
wherein one of a source and a drain of the seventh transistor is directly connected to the gate of the second transistor,
wherein a gate of the seventh transistor is directly connected to the gate of the first transistor,
wherein one of a source and a drain of the eighth transistor is directly connected to the gate of the first transistor,
wherein the other of the source and the drain of the second transistor, the other of the source and the drain of the third transistor, the other of the source and the drain of the fifth transistor, the other of the source and the drain of the seventh transistor, and the other of the source and the drain of the eighth transistor are directly connected to one another,
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring capable of supplying a first signal,
wherein a potential of the gate of the second transistor is changed depending on a potential of a second wiring capable of supplying a second signal, and
wherein the second wiring is not electrically connected to the first wiring.

15 more elements

A semiconductor device comprising:

a driver circuit,
wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor,
wherein one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor comprises a channel formation region that comprises an amorphous silicon,
wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is directly connected to one of a source and a drain of the third transistor,
wherein one of a source and a drain of the fourth transistor is directly connected to one of a source and a drain of the fifth transistor,
wherein one of a source and a drain of the sixth transistor is directly connected to the one of the source and the drain of the fifth transistor,
wherein the other of the source and the drain of the fourth transistor is directly connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the first transistor is directly connected to the one of the source and the drain of the fourth transistor,
wherein a gate of the second transistor is directly connected to a gate of the fifth transistor,
wherein a gate of the third transistor is directly connected to a gate of the sixth transistor,
wherein a gate of the fourth transistor is directly connected to the other of the source and the drain of the fourth transistor,
wherein one of a source and a drain of the seventh transistor is directly connected to the gate of the second transistor,
wherein a gate of the seventh transistor is directly connected to the gate of the first transistor,
wherein one of a source and a drain of the eighth transistor is directly connected to the gate of the first transistor,
wherein the other of the source and the drain of the second transistor, the other of the source and the drain of the third transistor, the other of the source and the drain of the fifth transistor, the other of the source and the drain of the seventh transistor, and the other of the source and the drain of the eighth transistor are directly connected to one another,
wherein one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor comprises:
a gate electrode;
a gate insulating film over the gate electrode;
a first semiconductor layer over the gate insulating film;
a second semiconductor layer over the first semiconductor layer, the second semiconductor layer comprising a first region, a second region, a third region, a fourth region, and a fifth region;
a third semiconductor layer over the second semiconductor layer;
a fourth semiconductor layer over the second semiconductor layer;
a source electrode over the third semiconductor layer;
and
a drain electrode over the fourth semiconductor layer,
wherein the first region overlaps with the first semiconductor layer, does not overlap with the third semiconductor layer, and does not overlap with the fourth semiconductor layer,
wherein the second region is located between the first semiconductor layer and the third semiconductor layer, and overlaps with the source electrode,
wherein the third region is located between the first semiconductor layer and the third semiconductor layer, and does not overlap with the source electrode,
wherein the fourth region is located between the first semiconductor layer and the fourth semiconductor layer, and overlaps with the drain electrode,
wherein the fifth region is located between the first semiconductor layer and the fourth semiconductor layer, and does not overlap with the drain electrode,
wherein a thickness of the second semiconductor layer in the first region is smaller than a thickness of the second semiconductor layer in the second region,
wherein a thickness of the second semiconductor layer in the first region is smaller than a thickness of the second semiconductor layer in the third region,
wherein a thickness of the second semiconductor layer in the first region is smaller than a thickness of the second semiconductor layer in the fourth region, and
wherein a thickness of the second semiconductor layer in the first region is smaller than a thickness of the second semiconductor layer in the fifth region.

32 more elements

A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;
wherein one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor comprises a channel formation region comprising an amorphous silicon,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the one of the source and the drain of the fifth transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the fourth transistor,
wherein a gate of the second transistor is electrically connected to a gate of the fifth transistor,
wherein a gate of the third transistor is electrically connected to a gate of the sixth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor,
wherein a gate of the seventh transistor is electrically connected to the gate of the first transistor,
wherein the gate of the third transistor is electrically connected to a wiring capable of supplying clock signal,
wherein one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor comprises:
a gate electrode;
a gate insulating film over the gate electrode;
a first semiconductor layer over the gate insulating film;
a second semiconductor layer over the first semiconductor layer, the second semiconductor layer comprising a first region, a second region, a third region, a fourth region, and a fifth region;
a third semiconductor layer over the second semiconductor layer;
a fourth semiconductor layer over the second semiconductor layer;
a source electrode over the third semiconductor layer;
and
a drain electrode over the fourth semiconductor layer,
wherein the first region overlaps with the first semiconductor layer, does not overlap with the third semiconductor layer, and does not overlap with the fourth semiconductor layer,
wherein the second region is located between the first semiconductor layer and the third semiconductor layer, and overlaps with the source electrode,
wherein the third region is located between the first semiconductor layer and the third semiconductor layer, and does not overlap with the source electrode,
wherein the fourth region is located between the first semiconductor layer and the fourth semiconductor layer, and overlaps with the drain electrode,
wherein the fifth region is located between the first semiconductor layer and the fourth semiconductor layer, and does not overlap with the drain electrode,
wherein a thickness of the second semiconductor layer in the first region is smaller than a thickness of the second semiconductor layer in the second region,
wherein a thickness of the second semiconductor layer in the first region is smaller than a thickness of the second semiconductor layer in the third region,
wherein a thickness of the second semiconductor layer in the first region is smaller than a thickness of the second semiconductor layer in the fourth region, and
wherein a thickness of the second semiconductor layer in the first region is smaller than a thickness of the second semiconductor layer in the fifth region.

30 more elements

A semiconductor device comprising:

a pixel;
a driver circuit electrically connected to the pixel,
wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;
wherein one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor comprises a channel formation region comprising an amorphous silicon,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the one of the source and the drain of the fifth transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the fourth transistor,
wherein a gate of the second transistor is electrically connected to a gate of the fifth transistor,
wherein a gate of the third transistor is electrically connected to a gate of the sixth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor,
wherein a gate of the seventh transistor is electrically connected to the gate of the first transistor,
wherein the gate of the third transistor is electrically connected to a wiring capable of supplying clock signal,
wherein one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor comprises:
a gate electrode;
a gate insulating film over the gate electrode;
a first semiconductor layer over the gate insulating film;
a second semiconductor layer over the first semiconductor layer, the second semiconductor layer comprising a first region, a second region, a third region, a fourth region, and a fifth region;
a third semiconductor layer over the second semiconductor layer;
a fourth semiconductor layer over the second semiconductor layer;
a source electrode over the third semiconductor layer;
and
a drain electrode over the fourth semiconductor layer,
wherein the first region overlaps with the first semiconductor layer, does not overlap with the third semiconductor layer, and does not overlap with the fourth semiconductor layer,
wherein the second region is located between the first semiconductor layer and the third semiconductor layer, and overlaps with the source electrode,
wherein the third region is located between the first semiconductor layer and the third semiconductor layer, and does not overlap with the source electrode,
wherein the fourth region is located between the first semiconductor layer and the fourth semiconductor layer, and overlaps with the drain electrode,
wherein the fifth region is located between the first semiconductor layer and the fourth semiconductor layer, and does not overlap with the drain electrode,
wherein a thickness of the second semiconductor layer in the first region is smaller than a thickness of the second semiconductor layer in the second region,
wherein a thickness of the second semiconductor layer in the first region is smaller than a thickness of the second semiconductor layer in the third region,
wherein a thickness of the second semiconductor layer in the first region is smaller than a thickness of the second semiconductor layer in the fourth region, and
wherein a thickness of the second semiconductor layer in the first region is smaller than a thickness of the second semiconductor layer in the fifth region.

32 more elements

A semiconductor device comprising:

a driver circuit,
wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;
wherein one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises a channel formation region that comprises an oxide semiconductor,
wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is directly connected to one of a source and a drain of the third transistor,
wherein one of a source and a drain of the fourth transistor is directly connected to one of a source and a drain of the fifth transistor,
wherein one of a source and a drain of the sixth transistor is directly connected to the one of the source and the drain of the fifth transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the first transistor is directly connected to the one of the source and the drain of the fourth transistor,
wherein a gate of the second transistor is directly connected to a gate of the fifth transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring capable of supplying a first signal,
wherein a potential of the gate of the second transistor is changed depending on a potential of a second wiring capable of supplying a second signal, and
wherein the second wiring is not electrically connected to the first wiring.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/062,265Filed 7 Mar 2016 · continuation
Priority: JP 2008-15740017 Jun 2008
Published: US 2016/0190174 A130 Jun 2016
Granted: 6 Nov 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G09G 3/3677
Details of drivers for scan electrodes: suitable for active matrices only
G11C 19/184
In combination with semiconductor elements, e.g. bipolar transistors, diodes: with field-effect transistors, e.g. MOS-FET
G11C 19/28
Digital stores in which the information is moved stepwise, e.g. shift registers: using semiconductor elements
G09G 2310/0286
Details of driving circuits: details of a shift registers arranged for use in a driving circuit

Family

Application12/477,338Parent of this continuation · filed 3 Jun 2009
Application13/675,077Parent of this continuation · filed 13 Nov 2012
US 8,314,765 B2Parent of this continuation · filed 20 Nov 2012
Application14/305,367Parent of this continuation · filed 16 Jun 2014
US 8,774,347 B2Parent of this continuation · filed 8 Jul 2014
Application14/644,372Parent of this continuation · filed 11 Mar 2015
US 9,036,767 B2Parent of this continuation · filed 19 May 2015
US 2016/0190174 A1Pre-grant publication · published 30 Jun 2016
US 9,311,876 B2Parent of this continuation
US 2009/0310734 A1Published application
US 2013/0069923 A1Published application
US 2014/0292629 A1Published application
US 2015/0255033 A1Published application
US 8,983,022 B2Related patent
US 10,121,435 B2This patent

From the US filing history. Foreign family members aren’t listed.

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Abstract

A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;
wherein one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises a channel formation region that comprises an oxide semiconductor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the one of the source and the drain of the fifth transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the fourth transistor,
wherein a gate of the second transistor is electrically connected to a gate of the fifth transistor,
wherein a gate of the third transistor is electrically connected to a gate of the sixth transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring capable of supplying a first signal,
wherein a potential of the gate of the second transistor is changed depending on a potential of a second wiring capable of supplying a second signal, and
wherein the second wiring is not electrically connected to the first wiring.

11 more elements

Facts

Application

15/062,265Filed 7 Mar 2016 · continuation

Priority

JP 2008-15740017 Jun 2008

Published

US 2016/0190174 A130 Jun 2016

Granted

6 Nov 2018

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G09G 3/3677
Details of drivers for scan electrodes: suitable for active matrices only
G11C 19/184
In combination with semiconductor elements, e.g. bipolar transistors, diodes: with field-effect transistors, e.g. MOS-FET
G11C 19/28
Digital stores in which the information is moved stepwise, e.g. shift registers: using semiconductor elements
G09G 2310/0286
Details of driving circuits: details of a shift registers arranged for use in a driving circuit

Family

Application12/477,338Parent of this continuation · filed 3 Jun 2009

Application13/675,077Parent of this continuation · filed 13 Nov 2012

US 8,314,765 B2Parent of this continuation · filed 20 Nov 2012

Application14/305,367Parent of this continuation · filed 16 Jun 2014

US 8,774,347 B2Parent of this continuation · filed 8 Jul 2014

Application14/644,372Parent of this continuation · filed 11 Mar 2015

US 9,036,767 B2Parent of this continuation · filed 19 May 2015

US 2016/0190174 A1Pre-grant publication · published 30 Jun 2016

US 9,311,876 B2Parent of this continuation

US 2009/0310734 A1Published application

US 2013/0069923 A1Published application

US 2014/0292629 A1Published application

US 2015/0255033 A1Published application

US 8,983,022 B2Related patent

US 10,121,435 B2This patent

From the US filing history. Foreign family members aren’t listed.