Stage circuit and scan driver using the same

A stage circuit comprising:

• an output unit configured to supply a voltage of a first node to a first output terminal, to supply an i-th (i is a natural number) carry signal to a second output terminal, and to supply an i-th scan signal to a third output terminal in response to the voltage of the first node, a voltage of a second node, and a first clock signal supplied to a first input terminal;
• a controller configured to control the voltage of the second node in response to the first clock signal supplied to the first input terminal;
• a pull-up unit configured to control the voltage of the first node in response to a carry signal of a previous stage supplied to a second input terminal and a voltage of a first node of the previous stage supplied to a third input terminal;
• and
• a pull-down unit configured to control the voltage of the first node in response to the voltage of the second node and a carry signal of a next stage supplied to a fourth input terminal,
• wherein the pull-up unit comprises:
• a first transistor having a first electrode connected to the second input terminal and a gate electrode connected to the third input terminal;
• a second transistor having a first electrode and a gate electrode connected to a second electrode of the first transistor and a second electrode connected to the first node;
• a third transistor having a first electrode connected to the first electrode of the first transistor and a gate electrode and a second electrode connected to the second output terminal;
• and
• a fourth transistor having a first electrode and a gate electrode connected to the second input terminal and a second electrode connected to the first electrode of the first transistor.

A scan driver including stages respectively connected to scan lines and outputting one of a plurality of clock signals input from an external source as scan signals, wherein an i-th (i is a natural number) stage circuit among the stages comprises:

• an output unit configured to supply a voltage of a first node to a first output terminal, to supply an i-th carry signal to a second output terminal, and to supply an i-th scan signal to a third output terminal in response to the voltage of the first node, a voltage of a second node, and a first clock signal supplied to a first input terminal;
• a controller configured to control the voltage of the second node in response to the first clock signal supplied to the first input terminal;
• a pull-up unit configured to control the voltage of the first node in response to an (i−1)-th carry signal of a previous stage supplied to a second input terminal and a voltage of a first node of the previous stage supplied to a third input terminal;
• and
• a pull-down unit configured to control the voltage of the first node in response to the voltage of the second node and an (i+1)-th carry signal of a next stage supplied to a fourth input terminal,
• wherein the pull-up unit comprises:
• a first transistor having a first electrode connected to the second input terminal and a gate electrode connected to the third input terminal;
• a second transistor having a first electrode and a gate electrode connected to a second electrode of the first transistor and a second electrode connected to the first node;
• and
• a third transistor having a first electrode connected to the second electrode of the first transistor and a gate electrode and a second electrode connected to the second output terminal.

A scan driver including stages respectively connected to scan lines and outputting one of a plurality of clock signals input from an external source as scan signals, wherein an i-th (i is a natural number) stage circuit among the stages comprises:

• an output unit configured to supply a voltage of a first node to a first output terminal, to supply an i-th carry signal to a second output terminal, and to supply an i-th scan signal to a third output terminal in response to the voltage of the first node, a voltage of a second node, and a first clock signal supplied to a first input terminal;
• a controller configured to control the voltage of the second node in response to the first clock signal supplied to the first input terminal;
• a pull-up unit configured to control the voltage of the first node in response to an (i−1)-th carry signal of a previous stage supplied to a second input terminal and a voltage of a first node of the previous stage supplied to a third input terminal;
• and
• a pull-down unit configured to control the voltage of the first node in response to the voltage of the second node and an (i+1)-th carry signal of a next stage supplied to a fourth input terminal,
• wherein the pull-up unit comprises:
• a first transistor having a first electrode connected to the second input terminal and a gate electrode connected to the third input terminal;
• a second transistor having a first electrode and a gate electrode connected to a second electrode of the first transistor and a second electrode connected to the first node;
• a third transistor having a first electrode connected to the first electrode of the first transistor and a gate electrode and a second electrode connected to the second output terminal;
• and
• a fourth transistor having a first electrode and a gate electrode connected to the second input terminal and a second electrode connected to the first electrode of the first transistor.