Shift register and display device

A shift register, comprising:

• a primary circuit having an output terminal, a first and a second input terminals, and a first common terminal;
• and
• a secondary circuit electrically connected to the first common terminal, and including:
• an inverting circuit;
• and
• a pull-down circuit electrically connected to the inverting circuit, and including:
• a first transistor having a first top gate, a first bottom gate, a first first electrode and a first second electrode;
• a second transistor having a second top gate, a second bottom gate, a second first electrode and a second second electrode;
• a third transistor having a third top gate, a third bottom gate, a third first electrode and a third second electrode;
• a fourth transistor having a fourth top gate, a fourth bottom gate, a fourth first electrode and a fourth second electrode;
• a second and a third common terminals, wherein:
• the first first electrode and the fourth second electrode are electrically connected to the output terminal;
• the second second electrode and the third first electrode are electrically connected to the first common terminal;
• the first and the second bottom gates are electrically connected to the second common terminal;
• the third and the fourth bottom gates are electrically connected to the third common terminal;
• the first second electrode, the second first electrode, the third second electrode and the fourth first electrode are configured to receive a first signal having a first voltage level;
• and
• the first top gate, the second top gate, the third top gate and the fourth top gate are configured to receive a second signal having a second voltage level.

A shift register, comprising:

• a primary circuit having an output terminal, a first and a second input terminals, and a first common terminal;
• and
• a secondary circuit electrically connected to the first common terminal, and including:
• an inverting circuit;
• and
• a pull-down circuit electrically connected to the inverting circuit and including:
• a first transistor having a first top gate, a first bottom gate, a first first electrode and a first second electrode;
• a second transistor having a second top gate, a second bottom gate, a second first electrode and a second second electrode;
• a third transistor having a third top gate, a third bottom gate, a third first electrode and a third second electrode;
• a fourth transistor having a fourth top gate, a fourth bottom gate, a fourth first electrode and a fourth second electrode;
• a second common terminal;
• and
• a third common terminal, wherein:
• the first and the second bottom gates are electrically connected to the second common terminal, the first second and the second first electrodes are configured to receive a first signal having a first voltage level, the first and the second top gates are configured to receive a second signal having a second voltage level, and the second voltage level is higher than the first voltage level;
• the third and the fourth bottom gates are electrically connected to the third common terminal;
• the first first electrode and the fourth second electrode are electrically connected to the output terminal;
• the second second electrode and the third first electrode are electrically connected to the first common terminal;
• the third second electrode and the fourth first electrode are configured to receive the first voltage level;
• and
• the third top gate and the fourth top gate are configured to receive the second voltage level.