Active matrix substrate, display panel, and display device including the same

An active matrix substrate comprising a plurality of gate lines, and a plurality of data lines that intersect the plurality of gate lines, the active matrix substrate including a display area, the active matrix substrate further comprising:

• a plurality of drive circuits provided for the plurality of gate lines, respectively, each of the plurality of drive circuits switching a state of a respective gate line according to a control signal supplied thereto, to either one of a selected state for selection of the respective gate line and a non-selection state for non-selection of the respective gate line, wherein
• each of the plurality of drive circuits includes a first charging driving portion and a second charging driving portion,
• the first charging driving portion includes a switching element that is supplied with a first DC voltage signal corresponding to the selected state, the switching element of the first charging driving portion charging the gate line to a potential of the first DC voltage signal,
• the second charging driving portion includes a switching element that is supplied with a second DC voltage signal corresponding to the non-selected state and having a voltage lower than that of the first DC voltage signal, the switching element of the second charging driving portion charging the respective gate line to a potential of the second DC voltage signal, and
• at least one of the first charging driving portion and the second charging driving portion is in the display area,
• the gate lines are N in number (N is an integer),
• a first start pulse signal is input to the first charging driving portion in the first drive circuit provided with respect to the first gate line, among the drive circuits, and the first charging driving portion charges the first gate line to the potential of the first DC voltage signal according to the first start pulse signal,
• a second start pulse signal different from the first start pulse signal is input to the second charging driving portion in the first drive circuit, and the second charging driving portion charges the first gate line to the potential of the second DC voltage signal according to the second start pulse signal,
• the first charging driving portion in the n'th drive circuit provided with respect to the n'th gate line (2≤n≤N), among the drive circuits, is connected to the n−1'th gate line, and the first charging driving portion charges the n'th gate line to the potential of the first DC voltage signal according to the potential of the n−1'th gate line, and
• the second charging driving portion in the n'th drive circuit is connected to the second charging driving portion in the drive circuit provided with respect to the n−1'th gate line, and charges the n'th gate line to the potential of the second DC voltage signal according to the output potential of the second charging driving portion in the n−1'th drive circuit.