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US 10,121,412 B2Granted
Display device and timing controller
AssigneeLG Display Co., Ltd.
InventorJinsol Choi
Life of this patent
Estimating the term…
Abstract
Disclosed is a display device and a timing controller that can check the status of a display driving related unit, take a proper countermeasure according to the check result, and prevent an abnormal operation of the display driving related unit or prevent a failure in driving, damage to a device, and screen abnormality that may happen according to the abnormal operation of the display driving related unit.
Claims15
A display device comprising:
- a unit status check unit that outputs a status check command signal to a status check unit corresponding to a display driving related unit, receives a signal output from the status check unit as a feedback signal according to the status check command signal, and records a status bit value of the status check unit in a status register corresponding to the status check unit based on the feedback signal;
- a memory that stores the status bit value of the status register corresponding to the status check unit;
- and
- a controller that performs an abnormality response process step-by-step according to the number of times that the abnormal status bit value is continually recorded in the status register,
- wherein the controller performs a first step of the abnormality response process when the abnormal status bit value is first recorded in the status register, performs a second step of the abnormality response process when the abnormal status bit value is continually recorded in the status register more than two times and less than the number of times needed to confirm an abnormal status, and performs a third step of the abnormality response process when the abnormal status bit value is continually recorded in the status register more than the number of times needed to confirm an abnormal status,
- wherein the display driving related unit is one of a data driver integrated circuit, a gate driver integrated circuit, a power management integrated circuit and a gamma unit.
3 more elements
A timing controller comprising:
- a status register that corresponds to each of a plurality of status check units relevant to display driving related units;
- a unit status check unit that outputs a status check command signal to each of the plurality of status check units, receives a signal output from the corresponding status check unit as a feedback signal according to the status check command signal, and records a status bit value of the corresponding status check unit in a status register corresponding to the corresponding status check unit based on the feedback signal;
- and
- a controller that performs an abnormality response process step-by-step according to the number of times that the abnormal status bit value is continually recorded in the status register,
- wherein the controller performs a first step of the abnormality response process when the abnormal status bit value is first recorded in the status register, performs a second step of the abnormality response process when the abnormal status bit value is continually recorded in the status register more than two times and less than the number of times needed to confirm an abnormal status, and performs a third step of the abnormality response process when the abnormal status bit value is continually recorded in the status register more than the number of times needed to confirm an abnormal status,
- wherein the display driving related unit is one of a data driver integrated circuit, a gate driver integrated circuit, a power management integrated circuit and a gamma unit.
3 more elements
A display device comprising:
- a timing controller that determines the status of a display driving related unit based on an output signal of the display driving related unit and records a status bit value in a status register corresponding to the display driving related unit;
- a memory that stores the status register corresponding to the display driving related unit;
- and
- a controller that performs an abnormality response process step-by-step according to the number of times that the abnormal status bit value is continually recorded in the status register,
- wherein the controller performs a first step of the abnormality response process when the abnormal status bit value is first recorded in the status register, performs a second step of the abnormality response process when the abnormal status bit value is continually recorded in the status register more than two times and less than the number of times needed to confirm an abnormal status, and performs a third step of the abnormality response process when the abnormal status bit value is continually recorded in the status register more than the number of times needed to confirm an abnormal status,
- wherein the display driving related unit is one of a data driver integrated circuit, a gate driver integrated circuit, a power management integrated circuit and a gamma unit.
3 more elements
Dependencies are inferred from the claim text.