System and method for creating aliased mappings to minimize impact of cache invalidation
AssigneeNVIDIA Corporation
InventorJeffrey Bolz
Life of this patent
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Abstract
A parallel processor and a method of reducing texture cache invalidation are disclosed. In one embodiment, the parallel processor includes a cache configured to receive lines of data; and a parallel execution unit associated with the cache and configured to execute parallel counterparts of an operation. The parallel counterparts, when executed, are configured to create, in the cache, corresponding aliases of a line of data pertaining to the operation such that the parallel counterparts are operable to invalidate only the corresponding aliases.
Claims20
A parallel processor, comprising:
- a cache configured to receive data pertaining to an operation;
- and
- a parallel execution unit associated with said cache and configured to execute parallel counterparts of said operation such that, when executed in parallel, said parallel counterparts is configured to create in said cache multiple aliases for said data, each of said multiple aliases corresponding to a different copy of said data,
- wherein each of said parallel counterparts is operable to invalidate only one of said different copies of said data.
A method of reducing an impact of cache invalidation, comprising:
- executing, using a parallel processor, parallel counterparts of a surface operation in parallel, said operation pertaining to data in a cache;
- causing, with said parallel counterparts, multiple aliases for said data to be loaded into said cache, each of said multiple aliases corresponding to a different copy of said data;
- and
- allowing each of said parallel counterparts of said operation to invalidate only one of said different copies of said data.
A non-transitory computer readable medium storing a surface operation that is executable by a processor, said surface operation comprising:
- executing parallel counterparts of said surface operation in parallel, said operation pertaining to data in a cache;
- causing, with said parallel counterparts, multiple aliases for said data to be loaded into said cache, each of said multiple aliases corresponding to a different copy of said data;
- and
- allowing each of said parallel counterparts of said operation to invalidate only one of said different copies of said data.
Dependencies are inferred from the claim text.