Apparatus, method and article of manufacture for partially resisting hardware trojan induced data leakage in sequential logics

In a sequential logic circuit having at least two combinational logic circuit functions each having an output and at least one pair of logic inputs, a security method for use therewith, comprising the steps of:

• generating at least two random logic states each randomly comprising a logic state 1 or 0;
• encoding each logic input of said at least one pair of logic inputs with a Boolean operation on a preselected one of said at least two random logic states;
• selectively multiplexing said output of said at least two combinational logic circuit functions according to a logic state of said at least two random logic states;
• latching said multiplexed output of said at least two combinational logic circuit functions;
• exclusively OR'ing a first input comprising said multiplexed output of said at least two combinational logic circuit functions, with an encoded second input,
• wherein said second input is encoded by a step of performing said Boolean operation on a current clock cycle state and a prior clock cycle state of said preselected one of said at least two random logic states.

A secure logic chip as an article of manufacture comprising a logic portion and a security portion, wherein

• said logic portion comprises a plurality of combinational logic circuits each having inputs and an output;
• said security portion comprises:
• a random logic state generator producing two randomly generated logic states;
• a multiplexer,
• having as inputs said outputs of said combinational logic circuits;
• and
• having a selection among said inputs based upon the logic state of said two randomly generated logic states;
• a latch for latching an output of said multiplexer;
• and
• an exclusive OR for decoding an output of said latch as a function of at least one of said two randomly generated logic states;
• and
• wherein said logic portion and said security portion are manufactured as separate chips and thereafter functionally integrated into said secure logic chip;
• and
• wherein said logic portion and said secure portion are functionally integrated by:
• arrangement as a physical stack;
• and
• through-silicon-vias to establish electrical connections between said logic portion and said secure portion.

A semiconductor chip as an article of manufacture for securely encoding logic circuits, comprising:

• an array of security encoding cells fabricated onto said semiconductor chip, wherein each said cell further comprises:
• a multiplexer,
• having as inputs those outputs of said logic circuits to be securely encoded;
• and
• having a selection among said inputs based upon the logic state of one or more randomly generated logic states;
• a latch for latching an output of said multiplexer;
• and
• an exclusive OR for decoding an output of said latch as a function of said one or more randomly generated logic states;
• a crossbar structure for electrically interconnecting said one or more randomly generated logic states to all said security encoding cells in said semiconductor chip;
• and
• through-silicon-vias to establish electrical connections between said security encoding cells and said logic circuits.