Integrated fan-out package and layout method thereof

An integrated fan-out package, comprising:

• a die having an interconnect structure therein;
• and
• a fan-out substrate having a conductive redistribution layer structure therein and a plurality of first conductive bumps and a plurality of second conductive bumps on a first surface thereof,
• wherein the first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a conductive redistribution layer of the conductive redistribution layer structure, and the second conductive bumps are not in physical contact with the interconnect layer but in physical contact with the conductive redistribution layer, and
• wherein the interconnect layer of the interconnect structure comprises a plurality of first conductive lines, the conductive redistribution layer of the conductive redistribution layer structure comprises a plurality of second conductive lines, the first conductive lines of the die are, in a top view, non-parallel to the second conductive lines of the fan-out substrate, and in the top view, an area of a total of regions where the first conductive lines of the interconnect layer of the die are overlapped with the second conductive lines of the conductive redistribution layer of the fan-out substrate is smaller than a preset value determined by an integrated fan-out package performance according to capacitance and inductance information or a coupling effect between the die and the fan-out substrate, wherein the plurality of first conductive bumps and the plurality of second conductive bumps are overlapped with each of the fan-out substrate and the die.

An integrated fan-out package, comprising:

• a die having an interconnect structure therein;
• and
• a fan-out substrate having a conductive redistribution layer structure therein and a plurality of first conductive bumps and a plurality of second conductive bumps on a first surface thereof,
• wherein the first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a conductive redistribution layer of the conductive redistribution layer structure, and the second conductive bumps are not in physical contact with the interconnect layer but in physical contact with the conductive redistribution layer, and
• wherein the interconnect layer of the interconnect structure comprises a plurality of first conductive lines, the conductive redistribution layer of the conductive redistribution layer structure comprises a plurality of second conductive lines, at least some of the first conductive lines of the die are, in a top view, parallel to the second conductive lines of the fan-out substrate, and in the top view, an area of a total of regions where the first conductive lines of the interconnect layer of the die are overlapped with the second conductive lines of the conductive redistribution layer of the fan-out substrate is smaller than a preset value determined by an integrated fan-out package performance according to capacitance and inductance information or a coupling effect between the die and the fan-out substrate, wherein the plurality of first conductive bumps and the plurality of second conductive bumps are overlapped with each of the fan-out substrate and the die.