US 10,120,965 B2Granted

Waveform based reconstruction for emulation

AssigneeSynopsys, Inc.

InventorsJohnson Adaikalasamy, Gagan Vishal Jain, Stanislav Margolin

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Abstract

A disclosed system of an emulation environment performs a simulation to construct a waveform of a target signal based on signals traced by an emulator for a time frame including multiple clock cycles. In one embodiment, a simulation is performed in a manner that an input of the logic gate, in a first duration of the time frame at which an output of the logic gate depends on the input, is analyzed to obtain the output, and the input of the logic gate, in a second duration of the time frame at which the output of the logic gate is independent, is omitted. In one aspect, the input of the logic gate is simulated for the first duration based on a periodicity in a waveform of the input in the first duration.

Claims20

Dependent claims

A non-transitory computer readable medium storing instructions, the instructions when executed by one or more processors cause the one or more processors to:

receive, from an emulator, an emulation result of a design under test (DUT) for fabrication, the emulation result including waveforms of signals of the DUT traced by the emulator for a time frame based on emulation of the DUT, the time frame including a plurality of clock cycles;
determine a logic gate from a plurality of logic gates to be evaluated based on the waveforms of the signals of the DUT traced, the plurality of logic gates comprising logic gates included in the DUT;
simulate one or more logic gates coupled to an input signal of the logic gate for a first duration of the time frame;
omit simulation of the one or more logic gates for a second duration of the time frame;
generate an output waveform of an output signal of the logic gate for the time frame based on the simulation of the one or more logic gates for the first duration, the output signal of the logic gate not traced by the emulator;
and
verify the DUT based on the output waveform prior to fabricating the DUT.

4 more elements

A non-transitory computer readable medium storing instructions, the instructions when executed by one or more processors cause the one or more processors to:

determine a first duration of a time frame at which a waveform of a reference signal of a logic gate of a plurality of logic gates is in a first state and a second duration of the time frame at which the waveform of the reference signal is in a second state different from the first state, the time frame including a plurality of clock cycles, the waveform of the reference signal obtained based on an emulation result of a design under test (DUT) generated by an emulator, the plurality of logic gates comprising logic gates included in the DUT;
determine a periodicity in an input waveform of an input signal of the logic gate in the first duration;
generate an output waveform of an output signal of the logic gate for the time frame based on the determined periodicity in the first duration and irrespective of the input waveform of the input signal in the second duration, the output signal of the logic gate not traced by the emulator;
and
verify the DUT based on the output waveform prior to fabricating the DUT.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/278,659Filed 28 Sep 2016 · us provisional application
Priority: 30 Sep 2015
Published: US 2017/0091360 A130 Mar 2017
Granted: 6 Nov 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 30/331
Using simulation: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
G06F 30/3312
Using simulation: timing analysis
G06F 2119/12
Details relating to the type or aim of the analysis or the optimisation: timing analysis or timing optimisation
G06F
Computing and data processing

Family

Application62/235,483Us provisional application · filed 30 Sep 2015
US 2017/0091360 A1Pre-grant publication · published 30 Mar 2017
US 10,120,965 B2This patent

From the US filing history. Foreign family members aren’t listed.

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