Processor and method for dynamically allocating processing elements to front end units using a plurality of registers

A method for supporting multi-mode processing, comprising:

• determining, at a controller of a processor, that thread divergence occurs in response to a result of processing a conditional branch instruction detected by an active first front end unit;
• activating an additional front end unit;
• setting, at the controller, control information such that arbitrary processing elements, among a plurality of processing elements, are dynamically allocated between the active first front end unit and the activated additional front end unit, wherein a first processing element is allocated to the active first front end unit and a second processing element is allocated to the activated additional front end unit;
• and
• reallocating, upon termination of the thread divergence, the second processing element to the active first front end unit, and deactivating the activated additional front end unit,
• wherein the first processing element processes a first instruction decoded by the active first front end unit,
• the second processing element processes a second instruction decoded by the activated additional front end unit,
• the controller comprises a plurality of registers,
• each of the plurality of registers is associated with a corresponding front end unit among all front end units, and is configured to store processing element allocation information for the corresponding front end unit,
• each of the plurality of registers comprises a plurality of bit-areas,
• a total number of bit-areas in each of the plurality of registers is equal to a total number of the plurality of processing elements, and
• the plurality of bit-areas is configured to store the processing element allocation information of the corresponding front end unit.

A multimode processor, comprising:

• a controller comprising a plurality of registers, and configured to activate front end units of the multimode processor and set control information to dynamically allocate first arbitrary processing elements, among a plurality of processing elements, to an active first front end unit,
• wherein, in response to a determination by the controller that a thread divergence occurs, the controller is further configured to:
• activate a second front end unit;
• and
• set control information to allocate second arbitrary processing elements, which are not allocated to the active first front end unit, to the activated second front end unit,
• wherein the second arbitrary processing elements are configured to process an instruction decoded by the activated second front end unit,
• wherein each of the plurality of registers is associated with a corresponding front end unit among all front end units, and is configured to store processing element allocation information for the corresponding front end unit,
• wherein each of the plurality of registers comprises a plurality of bit-areas,
• wherein a total number of bit-areas in each of the plurality of registers is equal to total number of the plurality of processing elements, and
• wherein the plurality of bit-areas is configured to store the processing element allocation information of the corresponding front end unit.

A multimode processor, comprising:

• a plurality of front end units;
• a plurality of processing elements;
• and
• a controller comprising a plurality of registers,
• wherein the controller is configured to:
• determine that thread divergence occurs in response to a result of processing a conditional branch instruction detected by an active first front end unit among the plurality of front end units;
• perform, when it is determined by the controller that the thread divergence occurs,
• an activation of an additional front end unit, and
• a setting of control information to dynamically allocate arbitrary processing elements, among the plurality of processing elements, between the active first front end unit and the activated additional front end unit, wherein a first processing element is allocated to the active first front end unit and a second processing element is allocated to the activated additional front end unit;
• and
• reallocate, upon termination of the thread divergence, the second processing element to the active first front end unit, and deactivate the activated additional front end unit,
• wherein the first processing element processes a first instruction decoded by the active first front end unit,
• the second processing element processes a second instruction decoded by the activated additional front end unit,
• each of the plurality of registers is associated with a corresponding front end unit among the plurality of front end units, and is configured to store processing element allocation information for the corresponding front end unit,
• each of the plurality of registers comprises a plurality of bit-areas,
• a total number of bit-areas in each of the plurality of registers is equal to a total number of the plurality of processing elements, and
• the plurality of bit-areas is configured to store the processing element allocation information of the corresponding front end unit.