Circuit and method for handling write and read requests between a master circuit and a slave circuit in different clock domains

A circuit arrangement, comprising:

• a master circuit configured and arranged to issue write requests and read requests;
• a slave circuit configured and arranged to process the write requests and read requests;
• and
• a transaction adapter coupling the master circuit to the slave circuit, wherein the transaction adapter includes:
• a first write FIFO circuit configured and arranged to receive and buffer write addresses of the write requests from the master circuit and addressed to the slave circuit, wherein the first write FIFO circuit has a write port clocked by a first clock signal and a read port clocked by a second clock signal;
• a second write FIFO circuit configured and arranged to receive and buffer write data associated with the write addresses of the write requests, wherein the second write FIFO circuit has a write port clocked by the first clock signal and a read port clocked by the second clock signal;
• a read FIFO circuit configured and arranged to receive and buffer read addresses of the read requests from the master circuit and addressed to the slave circuit;
• and
• a write acknowledgement control circuit configured and arranged to transmit an acknowledgement to a write request to the master circuit before the slave circuit issues a response to the write request, wherein the write acknowledgement control circuit is further configured and arranged to transmit an acknowledgement to a write address received when the second clock signal is running at a first rate, and transmit an acknowledgement to a write address received when the second clock signal is stopped.

A method of processing requests from a master circuit to a slave circuit, comprising:

• storing in a first write FIFO circuit of a transaction adapter, write addresses of write requests from the master circuit and addressed to the slave circuit;
• inputting a first clock signal to a write port of the first write FIFO circuit and inputting a second clock signal to a read port of the first write FIFO circuit, wherein the first clock signal has signal attributes different from signal attributes of the second clock signal;
• storing in a second write FIFO circuit of the transaction adapter, write data associated with the write addresses of the write requests;
• inputting the first clock signal to a write port of the second write FIFO circuit and inputting the second clock signal to a read port of the second write FIFO circuit;
• storing in a read FIFO circuit of the transaction adapter, read addresses of read requests from the master circuit and addressed to the slave circuit;
• transmitting by the transaction adapter, an acknowledgement to a write request to the master circuit before the slave circuit issues a response to the write request;
• transmitting an acknowledgement to a write address received when the second clock signal is running at a first rate;
• transmitting an acknowledgement to a write address received when the second clock signal is stopped.