System and method for cache memory line fill using interrupt indication
AssigneeNXP USA, Inc.
InventorsMichael Rohleder, Stefan Singer, Josef Fuchs
Life of this patent
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AssigneeNXP USA, Inc.
InventorsMichael Rohleder, Stefan Singer, Josef Fuchs
Estimating the term…
An embedded computer system includes a processor, an interrupt source, an interrupt controller and a cache memory subsystem. In response to a request from the processor to read a data element, the cache memory subsystem fills cache lines in a cache memory with data elements read from an upper-level memory. While filling a cache line the cache memory subsystem is unable to respond to a second request from the processor which also requires a cache line fill. In response to receiving an indication from an interrupt source, the interrupt controller provides an indication substantially simultaneously to the processor and to the cache memory subsystem. In response to receiving the indication from the interrupt controller, the cache memory subsystem terminates a cache line fill and prepares to receive another request from the processor.
An information processing system, comprising:
A method, comprising:
A system, comprising:
Dependencies are inferred from the claim text.