US 10,120,816 B2Granted

Bad column management with data shuffle in pipeline

AssigneeSanDisk Technologies LLC

InventorsWanfang Tsai, Yan Li

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Abstract

Systems and methods for controlling data flow and data alignment using data expand and compress circuitry arranged between a variable data rate bi-directional first in, first out (FIFO) buffer and one or more memory arrays to compensate for bad column locations within the one or more memory arrays are described. The bi-directional FIFO may have a variable data rate with the array side and a fixed data rate with a serializer/deserializer (SERDES) circuit that drives input/output (I/O) circuitry. The data expand and compress circuitry may pack and unpack data and then align the data passing between the one or more memory arrays and the bi-directional FIFO using a temporary buffer, data shuffling logic, and selective pipeline stalls.

Claims20

Dependent claims

An apparatus, comprising:

an input register configured to store a first set of data from one or more memory arrays;
a temporary buffer;
a control circuit configured to write a subset of the first set of data to the temporary buffer, the input register configured to store a second set of data from the one or more memory arrays;
an output register;
and
the control circuit configured to detect that the second set of data does not include data associated with a bad column within the one or more memory arrays and configured to write the subset of the first set of data from the temporary buffer to the output register in response to the detection that the second set of data does not include data associated with a bad column, the control circuit configured to write a first subset of the second set of data from the input register to the output register and configured to write a second subset of the second set of data from the input register to the temporary buffer.

3 more elements

An apparatus, comprising:

an input register configured to store a second set of data to be written to one or more memory arrays;
a temporary buffer;
an output register;
and
a control circuit configured to detect that the output register does not have a data mapping to a bad column within the one or more memory arrays and configured to write a subset of a first set of data from the temporary buffer to the output register in response to detection that the output register does not have a data mapping to a bad column within the one or more memory arrays, the control circuit configured to write a first subset of the second set of data from the input register to the output register and configured to write a second subset of the second set of data from the input register to the temporary buffer.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/458,561Filed 14 Mar 2017 · us provisional application
Priority: 20 Jul 2016
Published: US 2018/0024948 A125 Jan 2018
Granted: 6 Nov 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification20 codes

G06F 13/1673
Details of memory controller: using buffers
G06F 3/061
Specifically adapted to achieve a particular effect: improving I/O performance
G06F 3/0655
Making use of a particular technique: vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more…
G06F 3/0688
Plurality of storage devices: non-volatile semiconductor memory arrays

Family

Application62/364,519Us provisional application · filed 20 Jul 2016
Application62/365,180Us provisional application · filed 21 Jul 2016
US 2018/0024948 A1Pre-grant publication · published 25 Jan 2018
US 10,120,816 B2This patent

From the US filing history. Foreign family members aren’t listed.

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