US 10,120,808 B2 · Apparatus having cache memory disposed in a memory transaction path between interconnect circuitry and a non-volatile memory, and corresponding method

Abstract

A data processing system includes interconnect circuitry providing a plurality of memory transaction paths between one or more transaction masters, including a processor, debugging circuitry and a DMA unit, and one or more transaction slaves including a non-volatile memory, a DRAM memory and an I/O interface. A cache memory is provided between the interconnect circuitry and the non-volatile memory. This cache memory may be a two way set associative cache memory. The cache memory may serve as a read-only cache memory. A cache miss will result in a line fill of a cache line including the target data which was missed. If prefetching is enabled for the cache memory and the transaction was attempting to read a program instruction, then a prefetch operation may be performed in which a further contiguous cache line of data is also fetched into the cache memory upon the cache miss.

Claims18

Dependent claims

Apparatus for processing data, comprising:

interconnect circuitry to provide a plurality of memory transaction paths between one or more transaction masters and one or more transaction slaves;
wherein:
said one or more transaction slaves comprise a non-volatile memory to store data, and
said one or more transaction masters comprise a processor to perform processing operations at least partially specified by program instructions stored in said non-volatile memory;
and further comprising
a cache memory disposed in a memory transaction path between said interconnect circuitry and said non-volatile memory to cache data read from said non-volatile memory, wherein:
said cache memory is responsive to a non-cacheable signal accompanying a memory transaction and identifying that said memory transaction is a non-cacheable transaction to non-cacheable data to bypass operation of said cache memory in servicing said non-cacheable transaction.

4 more elements

Dependencies are inferred from the claim text.

Apparatus having cache memory disposed in a memory transaction path between interconnect circuitry and a non-volatile memory, and corresponding method

Life of this patent

Apparatus having cache memory disposed in a memory transaction path between interconnect circuitry and a non-volatile memory, and corresponding method

Life of this patent

Abstract

Claims18