Multi-level system memory with near memory scrubbing based on predicted far memory idle time

A computing system, comprising:

• one or more processing cores;
• a networking interface;
• a multi-level system memory;
• a memory controller to interface to the multi-level system memory, the memory controller comprising least recently used (LRU) circuitry to keep track of least recently used cache lines kept in a higher level of the multi-level system memory, the memory controller comprising idle time predictor circuitry to predict idle times of a lower level of the multi-level system memory, the memory controller to write one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory in response to the idle time predictor circuitry indicating that a currently observed idle time of the lower level of the multi-level system memory is expected to be long enough to accommodate the write of the one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory.

A method, comprising:

• tracking least recently used cache lines in a memory side cache of a multi-level system memory;
• predicting a time length of a currently observed idle time in a lower level of the multi-level system memory that the memory side cache acts as a cache for;
• and,
• writing one or more of the least recently used cache lines from the memory side cache into the lower level of the multi-level system memory in response to the time length being deemed sufficiently long to accommodate the writing of the one or more of the least recently used cache lines from the memory side cache into the lower level of the multi-level system memory.