Hybrid tracking of transaction read and write sets
AssigneeInternational Business Machines Corporation
InventorsMichael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
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AssigneeInternational Business Machines Corporation
InventorsMichael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
Estimating the term…
Tracking a processor instruction is provided to limit a speculative mis-prediction. A non-speculative read set indication and/or write set indication are maintained for a transaction. The indication(s) are stored in cache. In addition, a queue(s) of at least one address corresponding to a speculatively executed instruction is maintained. For a received request from a processor, a transaction resolution process takes place, and a resolution is performed if an address match in the queue is detected. The resolution includes to hold a response to the receive request until the speculative instruction is committed or flushed.
A computer system comprising:
A computer program product for tracking a processor instruction, the computer program product comprising a computer readable storage medium having program code embodied therewith, the program code executable by a processing unit to:
A method for tracking a processor instruction comprising:
Dependencies are inferred from the claim text.