Transactional memory coherence control

A computer program product, the computer program product comprising:

• a processing circuit;
• one or more computer readable storage media device, said computer readable storage media device being readable by said processing circuit;
• wherein said computer readable storage media device store instructions for execution by said processing circuit for performing a method comprising, in a transactional memory environment comprising a plurality of processors:
• identifying one or more coherence privilege state indicators, said coherence privilege state indicators (i) being associated with said one or more selected processors, (ii) indicate a level of privilege associated with the one or more selected processors for coherence control interactions with other processors, and (iii) have at least three possible settings with at least one setting being based on a priority of said one or more selected processors;
• determining a coherence privilege behavioral pattern for said one or more selected processors based on said one or more coherence privilege state indicators, wherein the coherence privilege behavioral pattern (i) is based on the level of privilege and (ii) includes at least three sets of rules that respectively govern, at least in part, how transactions are processed by said one or more selected processors during at least three sequential time periods of operation for said one or more selected processors;
• and
• processing a transaction by said one or more selected processors based, at least in part, on the coherence privilege behavioral pattern.