US 10,120,798 B1 · Dynamic FPGA re-configuration using a virtual FPGA controller

Abstract

Technologies for field-programmable gate array (FPGA) processing include a computing device having a field-programmable gate array (FPGA) and a virtual FPGA controller (VFC). The computing device generates a user-specific platform profile (PP) that identifies one or more FPGA applications to be instantiated. The computing device synthesizes each FPGA application identified by the PP to generate a bit stream image that is associated with the PP and saves the bit stream image in a profile storage of the computing device. The computing device generates a virtual memory address that is indicative of the identified FPGA applications in response to saving the bit stream image. The VFC translates the virtual memory address to a user segment of the FPGA and a logical element (LE) offset within the user segment. The FPGA executes the bit stream associated with the PP with the FPGA at the LE offset. Other embodiments are described and claimed.

Claims24

Dependent claims

A computing device for field-programmable gate array (FPGA) processing, the computing device comprising:

a field-programmable gate array (FPGA);
a platform builder to generate a user-specific platform profile that identifies one or more FPGA applications to be instantiated;
a stream builder to (i) synthesize each FPGA application of the one or more FPGA applications identified by the user-specific platform profile to generate a bit stream image that is associated with the user-specific platform profile, and (ii) save the bit stream image in a profile storage of the computing device;
a system scheduler to generate a virtual memory address that is indicative of the one or more FPGA applications in response to saving of the bit stream image;
and
a virtual FPGA (VFPGA) controller to translate the virtual memory address to a user segment of the FPGA and a logical element (LE) offset within the user segment,
wherein the FPGA is to execute the bit stream image associated with the user-specific platform profile with the FPGA at the LE offset.

4 more elements

One or more non-transitory, machine readable storage media comprising a plurality of instructions that in response to being executed cause a computing device to:

generate a user-specific platform profile that identifies one or more FPGA applications to be instantiated;
synthesize each FPGA application of the one or more FPGA applications identified by the user-specific platform profile to generate a bit stream image that is associated with the user-specific platform profile;
save the bit stream image in a profile storage of the computing device;
generate a virtual memory address that is indicative of the one or more FPGA applications in response to saving the bit stream image;
translate, by a virtual field-programmable gate array (VFPGA) controller of the computing device, the virtual memory address to a user segment of a FPGA of the computing device and a logical element (LE) offset within the user segment;
and
execute, by the FPGA, the bit stream image associated with the user-specific platform profile at the LE offset.

4 more elements

Dependencies are inferred from the claim text.

Dynamic FPGA re-configuration using a virtual FPGA controller

Life of this patent

Dynamic FPGA re-configuration using a virtual FPGA controller

Life of this patent

Abstract

Claims24