Techniques for detecting race conditions

An apparatus to detect race conditions comprising:

• a hardware processor component, comprising a monitoring unit;
• a trigger component stored in a memory which when executed by the processor component causes the monitoring unit to detect a cache event arising from a race condition between accesses to a piece of data and to capture an indication of a state of the processor component to generate monitoring data in response to an occurrence of the cache event, the cache event comprising a read-for-ownership (RFO) cache event or a hit-modified (HITM) cache event based on a cache coherency mechanism, and the indication of the state comprising an address of an instruction pointer of the processor component, a type of the cache event indicating whether the cache event is a RFO cache event or a HITM cache event, and an identifier of a core to enable debugging;
• a counter component for execution by the processor component to configure a counter of the monitoring unit to enable capture of the indication of the state of the processor component at a frequency less than every occurrence of the cache event;
• and
• a filter component for execution by the processor component to:
• determine whether the race condition is between a first access to the piece of data by a first portion of an application routine executed by the processor component and a second access to the piece of data by a second portion of the application routine based on an identifier of at least one of the first portion, the second portion, a core of the processor component that executes one of the first and second portions, or a thread of execution of one of the first and second portions, and
• remove the indication from the monitoring data based on the cache event not arising from the race condition between the first access to the piece of data by the first portion of the application routine executed by the processor component and the second access to the piece of data by the second portion of the application routine to generate reduced data comprising a subset of multiple indications of the state of the processor component of the monitoring data.

An apparatus to detect race conditions comprising:

• a first hardware processor component;
• a second hardware processor component;
• a trigger component stored in a memory which when executed by the processor components configure a monitoring unit of the first hardware processor component to detect a cache event associated with a race condition between accesses to a piece of data and to capture a first indication of a state of the first hardware processor component as a first monitoring data in response to an occurrence of the cache event, and to configure a monitoring unit of the second hardware processor component to detect the cache event and to capture a second indication of a state of the second hardware processor component as a second monitoring data in response to an occurrence of the cache event, the cache event comprising a read-for-ownership (RFO) cache event or a hit-modified (HITM) cache event based on a cache coherency mechanism;
• and
• a filter component to:
• determine whether the race condition is between first and second portions of an application routine based on an identifier of at least one of the first portion, the second portion, a core of the first hardware processor component that executes one of the first and second portions, a core of the second hardware processor component that executes one of the first and second portions, or a thread of execution of one of the first and second portions, and
• remove at least one of the first indication and the second indication in a reduced data based on the cache event not arising from the race condition between access to the piece of data by the first portion of an application routine executed by one of the first and second hardware processor components and the access to the piece of data by the second portion of the application routine executed by one of the first and second hardware processor components.

At least one non-transitory machine-readable storage medium comprising instructions that when executed by a processor component, cause the processor component to:

• detect a cache event arising from a race condition between accesses to a piece of data by at least one application routine executed by the processor component, the cache event comprising a read-for-ownership (RFO) cache event or a hit-modified (HITM) cache event based on a cache coherency mechanism;
• recurringly capture an indication of a state of the processor component as monitoring data in response to an occurrence of the cache event at a selected interval of multiple occurrences of the cache event, each instance of the indication of the state comprising an address of an instruction pointer of the processor component and a type of the cache event indicating whether the cache event is a RFO cache event or a HITM cache event;
• determine whether the race condition is a read operation of a first portion of the application routine and a write operation of a second portion of the at least one application routine based on an identifier of at least one of the first portion, the second portion, a core of the processor component that executes one of the first and second portions, or a thread of execution of one of the first and second portions;
• and
• remove the indication from the monitoring data based on the cache event not arising from the race condition between the read operation of the first portion of the application routine and the write operation of a second portion of the application routine to generate a reduced data comprising a subset of multiple indications of the state of the processor component of the monitoring data.