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US 10,120,750 B2Granted
Cache memory, error correction circuitry, and processor system
AssigneeKabushiki Kaisha Toshiba
InventorsSusumu Takeda, Hiroki Noguchi, Kazutaka Ikegami, Shinobu Fujita
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Abstract
A cache memory includes cache memory circuitry that is accessible per cache line and a redundant-code storage that stores one or more numbers of first redundant codes to be used for error correction of cache line data stored in the cache memory circuitry per cache line and one or more numbers of second redundant codes to be used for error detection of a part of the cache line data.
Claims19
A cache memory comprising:
- cache memory circuitry that is accessible per cache line;
- and a redundant-code storage that stores:
- one or more numbers of first redundant codes to be used for error correction of cache line data stored in the cache memory circuitry per cache line, one or more numbers of second redundant codes to be used for error detection of critical data included in a part of the cache line data, and identification information to identify data corresponding to the second redundant codes, wherein the critical data comprises at least one of data corresponding to an address in a head side of the cache line, data accessed recently by a processor in the cache line, and a part of data selected in descending order of being more recently accessed by the processor core in the cache line.
An error correction circuitry comprising:
- error correction circuitry to perform error correction per cache line based on a first redundant code corresponding to cache line data stored in a cache memory per cache line;
- and error detection circuitry to perform error detection of the critical data based on a second redundant code corresponding to the critical data included in a part of the cache line data, wherein the critical data comprises at least one of data corresponding to an address in a head side of the cache line, data accessed recently by a processor in the cache line, and a part of data selected in descending order of being more recently accessed by the processor core in the cache line.
A processor system comprising:
- a processor core;
- a first-level cache memory;
- and
- a layered cache memory than the first-level cache memory,
- wherein the layered cache memory comprises:
- a data cache;
- a tag that stores address information on data stored in the data cache;
- and
- a redundant-code storage that stores a first redundant code used for error correction of cache line data stored in the data cache per cache line, a second redundant code to be used for error detection of critical data included in a part of the cache line data, and identification information to identify data corresponding to the second redundant codes,
- wherein the critical data comprises at least one of data corresponding to an address in a head side of the cache line, data accessed recently by a processor in the cache line, and a part of data selected in descending order of being more recently accessed by the processor core in the cache line.
7 more elements
Dependencies are inferred from the claim text.