Hardware controlled instruction pre-fetching

A system for loading and executing a plurality of tasks under the control of an operating system (OS), the system comprising:

• a computer processor circuit configured to execute software instructions for the OS and the plurality of tasks;
• a memory circuit configured to store the software instructions and coupled to the computer processor circuit to provide the software instructions to the computer processor circuit;
• a hardware loader circuit coupled to the memory circuit and configured to load software instructions into the memory circuit;
• and
• a task control circuit coupled to the computer processor circuit and the memory circuit and configured to:
• maintain, in response to task event information, a task information queue that includes task information for the plurality of tasks;
• identify, based upon the task information in the task information queue, a future task switch condition corresponding to a task switch time for a particular task of the plurality of tasks;
• determine, based upon the task information and the task switch time, a load start time for a set of instructions for the particular task by being further configured to:
• determine a load anticipation time for the particular task as a function of a size of the set of instructions and access time for a non-volatile memory circuit configured to store the set of instructions, and
• subtract the load anticipation time from the task switch time to result in the load start time;
• generate, in response to the load start time, a pre-fetch request to load the set of instructions for the particular task into the memory circuit;
• and
• forward the pre-fetch request to the hardware loader circuit.