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US 10,120,693 B2Granted
Fast multi-width instruction issue in parallel slice processor
AssigneeInternational Business Machines Corporation
InventorsSalma Ayub, Jeffrey C. Brownscheidle, Sundeep Chadha, Dung Q. Nguyen, Tu-An T. Nguyen, Salim A. Shah, Brian W. Thompto
Life of this patent
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Abstract
Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.
Claims20
A circuit arrangement, comprising:
- a plurality of parallel execution slices configured to execute instructions from one or more instruction streams, the plurality of parallel execution slices including first and second execution slices;
- a first issue logic circuit of the first execution slice, the first issue logic circuit configured to queue instructions dispatched to the first execution slice and to issue queued instructions for execution by the first execution slice, the first issue logic circuit further configured to queue a first portion of a multi-width instruction dispatched to the first execution slice;
- and
- a second issue logic circuit of the second execution slice, the second issue logic circuit configured to queue instructions dispatched to the second execution slice and to issue queued instructions for execution by the second execution slice, the second issue logic circuit further configured to queue a second portion of the multi-width instruction dispatched to the second execution slice;
- wherein the first issue logic circuit is further configured to initiate execution of the multi-width instruction by the first and second execution slices by:
- in a first issue cycle, communicating an early issue notification signal to the second issue logic circuit to cause the second issue logic circuit to prepare for issuance of the multi-width instruction during a second issue cycle;
- also in the first issue cycle, issuing a queued instruction other than the first portion of the multi-width instruction for execution by the first execution slice;
- and
- in the second issue cycle, issuing the first portion of the multi-width instruction for execution by the first execution slice;
- and
- wherein the first issue logic circuit is configured to initiate execution of the multi-width instruction in response to determining that the multi-width instruction is an oldest instruction queued by the first issue logic circuit, wherein the first issue logic circuit includes an age data structure that identifies an oldest instruction queued by the first issue logic circuit, and wherein the first issue logic circuit is configured to update the age data structure in connection with queuing each instruction dispatched to the first execution slice, and to access the age data structure to determine that the multi-width instruction is the oldest instruction queued by the first issue logic circuit.
8 more elements
A circuit arrangement, comprising:
- a plurality of parallel execution slices configured to execute instructions from one or more instruction streams, the plurality of parallel execution slices including first and second execution slices;
- a first issue logic circuit of the first execution slice, the first issue logic circuit configured to queue instructions dispatched to the first execution slice and to issue queued instructions for execution by the first execution slice, the first issue logic circuit further configured to queue a first portion of a multi-width instruction dispatched to the first execution slice;
- and
- a second issue logic circuit of the second execution slice, the second issue logic circuit configured to queue instructions dispatched to the second execution slice and to issue queued instructions for execution by the second execution slice, the second issue logic circuit further configured to queue a second portion of the multi-width instruction dispatched to the second execution slice;
- wherein the first issue logic circuit is further configured to initiate execution of the multi-width instruction by the first and second execution slices by:
- in a first issue cycle, communicating an early issue notification signal to the second issue logic circuit to cause the second issue logic circuit to prepare for issuance of the multi-width instruction during a second issue cycle;
- also in the first issue cycle, issuing a queued instruction other than the first portion of the multi-width instruction for execution by the first execution slice;
- and
- in the second issue cycle, issuing the first portion of the multi-width instruction for execution by the first execution slice;
- and
- wherein the early notification signal comprises an instruction tag (ITAG) signal broadcast to the second execution slice to resolve any dependencies with other instructions, wherein each of the first and second issue logic circuits is configured to broadcast an ITAG signal for each instruction issued thereby, and wherein the first issue logic circuit is further configured to broadcast the ITAG signal for the multi-width instruction a cycle early to actual issuance of the multi-width instruction by the first issue logic circuit.
8 more elements
A method of executing instructions in a processor core including a plurality of parallel execution slices configured to execute instructions from one or more instruction streams, the method comprising;
- in a first issue logic circuit of a first execution slice among the plurality of parallel execution slices, queuing instructions dispatched to the first execution slice and issuing queued instructions for execution by the first execution slice;
- in a second issue logic circuit of a second execution slice among the plurality of parallel execution slices, queuing instructions dispatched to the second execution slice and issuing queued instructions for execution by the second execution slice;
- queuing first and second portions of a multi-width instruction in the first and second issue logic circuits, respectively;
- and
- in the first issue logic circuit, initiating execution of the multi-width instruction by the first and second execution slices by:
- in a first issue cycle, communicating an early issue notification signal to the second issue logic circuit to cause the second issue logic circuit to prepare for issuance of the multi-width instruction during a second issue cycle;
- also in the first issue cycle, issuing a queued instruction other than the first portion of the multi-width instruction for execution by the first execution slice;
- and
- in the second issue cycle, issuing the first portion of the multi-width instruction for execution by the first execution slice;
- and
- wherein the first issue logic circuit is configured to initiate execution of the multi-width instruction in response to determining that the multi-width instruction is an oldest instruction queued by the first issue logic circuit, and wherein the method further comprises, within the first issue logic circuit:
- updating an age data structure that identifies an oldest instruction queued by the first issue logic circuit in connection with queuing each instruction dispatched to the first execution slice;
- and
- accessing the age data structure to determine that the multi-width instruction is the oldest instruction queued by the first issue logic circuit.
11 more elements
Dependencies are inferred from the claim text.