Context switching mechanism for a processor having a general purpose core and a tightly coupled accelerator

A method comprising:

• decoding a first instruction into a decoded first instruction, and a second instruction into a decoded second instruction with a decoder of a processor;
• executing the first decoded instruction with an execution unit of the processor to, for a thread executing on at least one accelerator of a plurality of accelerators of the processor that is to be placed in an inactive state, cause a save of context information for each of the at least one accelerator of the plurality of accelerators for the thread, and a save of a vector identifying the at least one accelerator corresponding to the context information;
• and
• executing the second decoded instruction with the execution unit of the processor to read the vector to determine which of the plurality of accelerators have saved context information for the thread, read the saved context information, and restore the saved context information into the at least one accelerator.

A non-transitory machine readable medium containing program instructions that when processed by a processor cause a method to be performed, the method comprising:

• decoding a first instruction into a decoded first instruction, and a second instruction into a decoded second instruction with a decoder of the processor;
• executing the first decoded instruction with an execution unit of the processor to, for a thread executing on at least one accelerator of a plurality of accelerators of the processor that is to be placed in an inactive state, cause a save of context information for each of the at least one accelerator of the plurality of accelerators for the thread, and a save of a vector identifying the at least one accelerator corresponding to the context information;
• and
• executing the second decoded instruction with the execution unit of the processor to read the vector to determine which of the plurality of accelerators have saved context information for the thread, read the saved context information, and restore the saved context information into the at least one accelerator.

A processor comprising:

• an accelerator;
• a decoder to decode a first instruction into a decoded first instruction, and a second instruction into a decoded second instruction;
• and
• an execution unit to:
• execute the first decoded instruction to, for a thread executing on the accelerator that is to be placed in an inactive state, cause a save of context information for the thread, and a save of a vector identifying the accelerator corresponding to the context information, and
• execute the second decoded instruction to read the vector to determine the accelerator to restore saved context information into for the thread, read the saved context information, and restore the saved context information into the accelerator.