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US 10,120,686 B2Granted
Eliminating redundant store instructions from execution while maintaining total store order
AssigneeIntel Corporation
InventorsVineeth Mekkat, Oleg Margulis, Ching-Tsun Chou, Youfeng Wu
Life of this patent
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Abstract
A processor includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, and a binary translator. The binary translator includes circuitry to identify a redundant store in the instruction stream, mark the start and end of a region of the instruction stream with the redundant store, remove the redundant store, and store an amended instruction stream with the redundant store removed.
Claims20
A processor, comprising:
- a front end including circuitry to decode instructions from an instruction stream;
- a data cache unit including circuitry to cache data for the processor;
- and
- a binary translator including circuitry to:
- identify a first redundant store in the instruction stream;
- mark a first start and a first end of a first region of the instruction stream with the first redundant store;
- remove the first redundant store;
- and
- store an amended instruction stream with the first redundant store removed.
6 more elements
A method, comprising:
- decoding instructions from an instruction stream;
- identifying a first redundant store in the instruction stream;
- marking a first start and a first end of a first region of the instruction stream with the first redundant store;
- removing the redundant store;
- and
- storing an amended instruction stream with the redundant store removed.
3 more elements
A data cache unit, comprising circuitry to:
- cache a first data drained, wherein the first data includes a first write set identifier;
- receive a first snoop;
- determine an address of the first snoop;
- compare the address of the first snoop to an address of the first data cached to determine whether the address of the first snoop matches the address of the first data cached;
- hold the first snoop based on the determination that the address of the first snoop matches the address of the first data cached;
- cache a second data drained, wherein the second data includes the first write set identifier and an end tag for a first region with total store elimination;
- and
- release the first snoop after the second data is cached.
5 more elements
Dependencies are inferred from the claim text.