Instructions and logic to perform mask load and store operations as sequential or one-at-a-time operations after exceptions and for un-cacheable type memory

A processor comprising:

• a decoder to decode a mask move instruction;
• and
• an execution unit to execute the mask move instruction to transfer unmasked data elements of a vector data element that is to include a plurality of packed data elements from a source location to a destination location, wherein the mask move instruction is to be executed subject to mask information in a vector mask register and the mask information is to indicate which of the plurality of packed data elements of the vector data element are the unmasked data elements, wherein the execution unit is to issue a full width operation for the plurality of packed data elements of the vector data element, and after an exception is to perform an individual operation for each of the unmasked data elements one at a time, wherein the mask move instruction is a mask load instruction, and the execution unit is to execute a speculative full width load operation as the full width operation to obtain and store the vector data element into a temporary storage and then determine that the exception occurred during the execution of the speculative full width load operation, and wherein the execution unit is to use a microcode handler to said perform the individual operation for said each of the unmasked data elements one at a time.

A processor comprising:

• a decoder to decode a mask load instruction;
• and
• an execution unit to execute the mask load instruction to load unmasked data elements of a vector data element that is to include a plurality of packed data elements from a source memory location to a destination register, wherein the mask load instruction is to be executed subject to mask information that is to indicate which of the plurality of packed data elements of the vector data element are the unmasked data elements, wherein the execution unit is to issue a full width load for the plurality of packed data elements of the vector data element, and when a type of memory for the full width load is un-cacheable the execution unit is to individually load each of the unmasked data elements one at a time.