Virtualization in a bi-endian-mode processor architecture

A computer system for processing vectors, the system comprising:

• a memory;
• and
• a bi-endian mode vector processor including a plurality of registers, each of the registers including a plurality of elements;
• the computer system configured to perform a method comprising:
• obtaining, by the processor, an instruction specifying an operation, the instruction further specifying one of the registers as a source register and one of the registers as a destination register;
• determining, by the processor, whether the instruction is an element-ordering-sensitive instruction;
• based on determining that the instruction is an element-ordering-sensitive instruction:
• obtaining, by the processor, an endian mode;
• and
• executing the instruction by the processor by performing the operation on the elements of the source register in accordance with the obtained endian mode and writing a result of the operation to the destination register;
• and
• based on determining that the instruction is not an element-ordering-sensitive instruction, executing the instruction by the processor by performing the operation on the elements of the source register in accordance with a first endian mode and writing a result of the operation to the destination register.