Compare and delay instructions
AssigneeInternational Business Machines Corporation
InventorsCharles W. Gainey, Jr., Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel
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AssigneeInternational Business Machines Corporation
InventorsCharles W. Gainey, Jr., Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel
Estimating the term…
A delay facility is provided in which program execution may be delayed until a predefined event occurs, such as a comparison of memory locations results in a true condition, a timeout is reached, an interruption is made pending or another condition exists. The delay facility includes one or more compare and delay machine instructions used to delay execution. The one or more compare and delay instructions may include a 32-bit compare and delay (CAD) instruction and a 64-bit compare and delay (CADG) instruction.
A computer program product for executing a machine instruction in a multi-threaded computing environment, said computer program product comprising:
A computer system for executing a machine instruction in a multi-thread computing environment, said computer system comprising:
Dependencies are inferred from the claim text.