Processor and method for outer product accumulate operations
AssigneeMicroUnity Systems Engineering, Inc.
InventorsCraig Hansen, John Moussouris, Alexia Massalin
Life of this patent
Estimating the term…
Abstract
A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations is disclosed.
Claims23
A processor for multiplying each one of a plurality n of multiplier operands each having a bit width of b bits and having an aggregate width of r bits where r=n*b with every one of a plurality n of multiplicand operands each having a bit width of b bits and having an aggregate width of r bits where r=n*b, the processor comprising:
- a register file having a bit width of r bits;
- an array of multiplier circuits arranged in rows and columns, each column coupled to receive one multiplier operand, each row coupled to receive one multiplicand operand, whereby each multiplier circuit receives a multiplier operand and a multiplicand operand and multiplies them together to provide a plurality n2 of multiplication results having an aggregate bit width greater than r bits;
- an array of adder circuits arranged in rows and columns, each adder circuit being coupled to a corresponding multiplier circuit;
- an array of accumulator circuits arranged in rows and columns, each accumulator circuit being coupled to a corresponding adder circuit;
- and
- wherein the multiplication result from each multiplier circuit is added to any previous multiplication result stored in the accumulator circuit and provided to the corresponding accumulator circuit and to thereby provide an accumulation result.
In a processor for multiplying each one of a plurality n of multiplier operands each having a bit width of b bits and having an aggregate width of r bits where r=n*b with every one of a plurality n of multiplicand operands each having a bit width of b bits and having an aggregate width of r bits where r=n*b, the processor comprising:
- a plurality n2 of tiles, each tile including:
- a multiplier circuit coupled to receive one of a plurality n of multiplier operands and one of a plurality n of multiplicand operands and multiply them together to provide a multiplication result having a bit width greater than r bits;
- an adder circuit coupled to the multiplier circuit;
- and
- an accumulator circuit coupled to the adder circuit;
- wherein the multiplication result from the multiplier circuit is provided to the adder circuit and added to any previous multiplication result stored in the accumulator circuit to thereby provide an accumulation result.
In a processor having an array of multiplier circuits arranged in rows and columns, an array of accumulator circuits arranged in rows and columns, and an array of adder circuits arranged in rows and columns, each multiplier circuit having an associated adder circuit and an associated accumulator circuit, the processor having a register file with a bit width of r bits, a method of performing an outer product of a vector multiplier operand and a vector multiplicand operand comprising:
- loading a first multiplier operand and a first multiplicand operand into each of the multiplier circuits, the multiplier circuit at location [i, j] in the array receiving first multiplier operand i and first multiplicand operand j;
- at each multiplier circuit performing a multiplication of the first multiplier operand i and the first multiplicand operand j to produce a first multiplication result i*j which is wider than r bits;
- and
- providing the first multiplication result to the associated adder circuit;
- adding the first multiplication result to any previous multiplication result to provide an accumulated multiplication result to the associated accumulator circuit.
Dependencies are inferred from the claim text.