Semiconductor memory device including a control circuit and at least two memory cell arrays

A method of notifying availability of data reads by a semiconductor memory device including first and second memory cell arrays and a control circuit, said method comprising:

• in response to a status read command, outputting first status information indicating whether the first memory cell array is in a ready state in which the control circuit is ready to receive a command to access the first memory cell array or a busy state in which the control circuit is not ready to receive the command to access the first memory cell array, and second status information indicating whether the second memory cell array is in a ready state in which the control circuit is ready to receive a command to access the second memory cell array or a busy state in which the control circuit is not ready to receive the command to access the second memory cell array;
• beginning a first process on the first memory cell array in response to a first command addressed to the first memory cell array if the first and second information indicates the first and second memory cell arrays are in the ready state, and beginning a second process on the second memory cell array according to a second command addressed to the second memory cell array if the first and second status information indicates at least the second memory cell array is in the ready state;
• and
• determining whether a core operation associated with the second command can be performed simultaneously with a core operation associated with the first command if the second command is received while the status information indicates the first memory cell array is in the busy state and the second memory cell array is in the ready state, the determination being made based on whether the core operation associated with the first command has started or not and a comparison of physical address targets of the first and second commands.