Method and design for dynamic management of descriptors for SGL operation

A controller for a non-volatile semiconductor storage device, comprising:

• a command random access memory (RAM) configured to store a plurality of commands received from a host system;
• a descriptor RAM;
• and
• a processing system having a back end configured to process active commands and a front end configured to:
• fetch DMA descriptors from the host system for each of the plurality of commands stored in the command RAM;
• store the DMA descriptors for each of the plurality of commands in free descriptor regions of a plurality of descriptor regions in the descriptor RAM;
• and
• maintain a dynamic descriptor list in the descriptor RAM for each of the plurality of commands, the dynamic descriptor list for each of the plurality of commands comprising occupied descriptor regions of the plurality of descriptor regions in the descriptor RAM having associated DMA descriptors,
• wherein at least one of the occupied descriptor regions includes multiple DMA descriptors and a single pointer to a next occupied descriptor region of the plurality of descriptor regions.

A non-transitory computer readable medium having stored thereon instructions that when executed by a processor cause the processor to perform a method of managing direct memory access (DMA) descriptors for a plurality of commands to a non-volatile semiconductor storage device, the method comprising:

• requesting DMA descriptors from a host system for each of the plurality of commands stored in a command random access memory (RAM);
• storing the DMA descriptors for each of the plurality of commands in free descriptor regions of a plurality of descriptor regions in a descriptor RAM of the non-volatile semiconductor storage device;
• and
• maintaining a dynamic descriptor list in the descriptor RAM for each of the plurality of commands, the dynamic descriptor list for each of the plurality of commands comprising occupied descriptor regions of the plurality of descriptor regions in the descriptor RAM having associated DMA descriptors,
• wherein at least one of the occupied descriptor regions includes multiple DMA descriptors and a single pointer to a next occupied descriptor region of the plurality of descriptor regions.