Apparatuses, systems, and methods for USB high-speed chirp detection

A method comprising:

• providing a first data path and a second data path from a bus host transceiver circuit to connect to a bus device;
• providing a squelch detection circuit with a first input and a second input;
• coupling the first data path to the first input of the squelch detection circuit separate from a first resistor and coupling the second data path to the second input of the squelch detection circuit separate from a second resistor when in a first mode, the first resistor comprising one of, and less than all of, a first plurality of pull-down resistors coupled to the first data path;
• and
• switching to a second mode to couple the first data path through the first resistor to the first input of the squelch detection circuit and couple the second data path through the second resistor to the second input of the squelch detection circuit when in a host reset period.

A computing system comprising:

• a processor coupled to a system memory;
• and
• a bus host transceiver circuit comprising:
• a first data path to connect to a bus device,
• a second data path to connect to the bus device,
• a squelch detection circuit with a first input and a second input, and
• a switching circuit to couple the first data path to the first input of the squelch detection circuit separate from a first resistor and couple the second data path to the second input of the squelch detection circuit separate from a second resistor when in a first mode, and switch to a second mode to couple the first data path through the first resistor to the first input of the squelch detection circuit and couple the second data path through the second resistor to the second input of the squelch detection circuit when in a host reset period, wherein the first resistor comprises one of, and less than all of, a first plurality of pull-down resistors coupled to the first data path.