Multiprocessing system with peripheral power consumption control

A method for sharing peripherals in a multiprocessor system comprising:

• using a first control register for a first peripheral, wherein the first control register includes an enable indicator for each processor in the multiprocessor system that can use the first peripheral;
• using a second control register for a second peripheral, wherein the second control register includes an enable indicator for each processor in the multiprocessor system that can use the second peripheral;
• generating a first low power request signal for the first peripheral when
• the enable indicator in the first control register for a first of the processors indicates the first of the processors has enabled use of the first peripheral, and
• the first of the processors has issued a first low power intent signal;
• and
• generating a second low power request signal for the second peripheral when
• the enable indicator in the second control register for the first or a second of the processors indicates the first or second of the processors has enabled use of the second peripheral, and
• the first of the processors has issued the first low power intent signal or the second of the processors has issued a second low power intent signal.

A multiprocessor system, comprising:

• a first control register for a first peripheral, wherein the first control register includes an enable indicator for each processor in the multiprocessor system that can use the first peripheral;
• a second control register for a second peripheral, wherein the second control register includes an enable indicator for each processor in the multiprocessor system that can use the second peripheral;
• acknowledgement generation circuitry configured to:
• generate a first low power acknowledgement signal from the first peripheral when
• the enable indicator in the first control register for a first of the processors indicates the first of the processors has enabled use of the first peripheral, and
• the first peripheral receives a first low power request signal,
• generate a second low power acknowledgement signal from the second peripheral when
• the enable indicator in the second control register for the first of the processors indicates the first of the processors has enabled use of the second peripheral, and
• the second peripheral receives the first low power request signal.