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US 10,120,275 B2Granted
Layout method of mask pattern, manufacturing method of a semiconductor device and exposure mask
AssigneeToshiba Memory Corporation
InventorsMasakazu Hamasaki, Yoshihiro Yanai, Michiya Takimoto, Naoki Sato, Satoshi Usui, Takaki Hashimoto
Life of this patent
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Abstract
According to one embodiment, a layout region of a mask pattern is divided into N (N is an integer of 2 or larger) units, a main pattern resolved by exposure light is arranged and sub patterns not resolved by the exposure light are arranged outside the main pattern such that distributions of attenuation amount of the exposure light in the divided layout regions are different.
Claims14
A layout method of mask pattern, comprising:
- dividing a layout region of a mask pattern into N (N is an integer of 2 or larger) units;
- and
- arranging a main pattern resolved by exposure light and arranging a periodic structure of sub patterns not resolved by the exposure light outside the main pattern such that distributions of attenuation amount of the exposure light in the divided layout regions are different each other.
An exposure mask, wherein
- a layout region of a mask pattern is divided into N (N is an integer of 2 or larger) units;
- and
- a main pattern resolved by exposure light is arranged and a periodic structure of sub patterns not resolved by the exposure light is arranged outside the main pattern such that distributions of attenuation amount of the exposure light in the divided layout regions are different.
Dependencies are inferred from the claim text.