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US 10,120,026 B2Granted
On-chip test pattern generation
AssigneeLantiq Beteiligungs-GmbH & Co. KG
InventorsHimanshu Kukreja, Shakil Ahmad
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Abstract
A chip is provided that includes an integrated circuit including a plurality of logic elements, wherein the plurality of logic elements is configured to form, in a test mode, a plurality of scan chains. The chip further includes an on-chip signal generator connected with the integrated circuit and configured to provide, in the test mode, a test pattern signal to the plurality of scan chains.
Claims10
A chip, comprising:
- an integrated circuit comprising a plurality of logic elements, wherein the plurality of logic elements is configured to form, in a test mode, a plurality of scan chains, and
- an on-chip signal generator connected with the integrated circuit and configured to provide, in the test mode, a test pattern signal to the plurality of scan chains,
- wherein the on-chip signal generator is configured to provide the test pattern signal having a codeword length N, and
- wherein plurality of logic elements is configured to form M scan chains,
- wherein N is smaller than M, and
- wherein the chip further comprises a decompressor configured to translate the test pattern signal having the codeword length of N into a decompressed test pattern signal having a codeword length of M, or
- wherein the on-chip signal generator is configured to provide the test pattern signal having a codeword length of N,
- wherein the plurality of logic elements is configured to form M scan chains, and
- wherein N equals M.
6 more elements
A chip, comprising:
- an integrated circuit comprising a plurality of logic elements, wherein the plurality of logic elements is configured to form, in a test mode, a plurality of scan chains, and
- an on-chip signal generator connected with the integrated circuit and configured to provide, in the test mode, a test pattern signal to the plurality of scan chains;
- an external clock pin connected with the signal generator and selectively connected with the integrated circuit,
- wherein the on-chip signal generator is configured to provide different states of the test pattern signal depending on a clock signal received via the external clock pin, and
- wherein each one of the plurality of logic elements is configured to toggle through different states depending on the clock signal and the test pattern signal.
2 more elements
A chip, comprising:
- an integrated circuit comprising a plurality of logic elements, wherein the plurality of logic elements is configured to form, in a test mode, a plurality of scan chains, and
- an on-chip signal generator connected with the integrated circuit and configured to provide, in the test mode, a test pattern signal to the plurality of scan chains;
- a plurality of external scan control pins selectively connected with the integrated circuit, and
- at least one switch configured to disconnect, in the test mode, the plurality of external scan control pins from the plurality of scan chains,
- wherein the at least one switch is configured to connect, in a further mode other than the test mode, the plurality of external scan control pins to the plurality of scan chains.
2 more elements
Dependencies are inferred from the claim text.