Multi-stage test response compactors

One or more non-transitory computer-readable media storing circuit design information for implementing an apparatus comprising:

• a first compactor comprising a plurality of first-compactor inputs and a first-compactor output;
• a register comprising a register input and a plurality of register outputs, the register input being coupled to the first-compactor output, the register being operable to load test response bits through the register input and to output the test response bits in parallel through the plurality of register outputs;
• a second compactor comprising a plurality of second-compactor inputs and a second-compactor output, the plurality of second-compactor inputs being coupled to the plurality of register outputs, the second compactor being a spatial compactor;
• a first set of masking logic coupled to the plurality of first-compactor inputs;
• a second set of masking logic coupled between the plurality of register outputs and the plurality of second-compactor inputs;
• and
• selection logic having one or more selection-logic inputs and a plurality of selection-logic outputs, the plurality of selection-logic outputs being coupled to respective inputs of the first set of masking logic and respective inputs of the second set of masking logic, the selection logic being operable to selectively control the first set of masking logic and the second set of masking logic in response to one or more masking instruction bits received at the one or more selection-logic inputs.

One or more non-transitory computer-readable media storing computer-executable instructions for causing a computer to create an apparatus comprising:

• a first compactor comprising a plurality of first-compactor inputs and a first-compactor output;
• a register comprising a register input and a plurality of register outputs, the register input being coupled to the first-compactor output, the register being operable to load test response bits through the register input and to output the test response bits in parallel through the plurality of register outputs;
• a second compactor comprising a plurality of second-compactor inputs and a second-compactor output, the plurality of second-compactor inputs being coupled to the plurality of register outputs, the second compactor being a spatial compactor;
• a first set of masking logic coupled to the plurality of first-compactor inputs;
• a second set of masking logic coupled between the plurality of register outputs and the plurality of second-compactor inputs;
• and
• selection logic having one or more selection-logic inputs and a plurality of selection-logic outputs, the plurality of selection-logic outputs being coupled to respective inputs of the first set of masking logic and respective inputs of the second set of masking logic, the selection logic being operable to selectively control the first set of masking logic and the second set of masking logic in response to one or more masking instruction bits received at the one or more selection-logic inputs.