3D tap and scan port architectures

An integrated circuit die comprising:

• (a) a first side including a test clock in signal contact point, a test mode select in signal contact point, a test reset in signal contact point, a test data in signal contact point, a test data out signal contact point, and an UP in signal contact point;
• (b) a CSU unit having an input coupled with the test clock in signal contact point, an input coupled to a test mode select in signal contact point, a capture shift output, an update output, and a scan clock output;
• (c) gating circuitry having an input coupled with the capture shift output, an input coupled with the update output, an input coupled with the scan clock output, an input coupled with the UP in signal contact point, a gated capture shift output, a gated update output, and a gated scan clock output;
• and
• (d) a test data register having an input coupled with the gated capture shift output, an input coupled with the gated update output, an input coupled with the gated scan clock output, an input coupled with the test reset in signal contact point, an input coupled with the test data in signal contact point, and an output coupled with the test data out signal contact point.