US 10,120,019 B2Granted

Automated method for analyzing a board having a plurality of FPGA components

AssigneeMentor Graphics Corporation

InventorsMatthieu Tuna, Zied Marrakchi, Christophe Alexandre

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Abstract

The disclosed technology relates to analyzing an electronic board having a plurality of FPGAs that are interconnected and programmed to implement a logic design. One example method comprises: setting up a graph representing the board; determining, for each FPGA, by means of an FPGA-specific static temporal analysis tool, the time for travelling over each path portion that passes through said FPGA, each travel time corresponding to the sum of the times for carrying out the logical operations applied to the signal in the FPGA; determining the inter-FPGA time for travelling over each inter-FPGA portion represented by a link in the graph; and determining the time for travelling over each path of the board by summing the intra-FPGA travel times and the inter-FPGA travel times associated with each link of the graph.

Claims20

Dependent claims

An automated method for developing a multi-FPGA prototype of an application-specific integrated circuit (ASIC), wherein the multi-FPGA prototype is implemented on an electronic board having a plurality of FPGA-type programmable chips (FPGAs) including a first FPGA and a second FPGA, the method comprising:

segmenting a netlist of the ASIC according to a number of the plurality FPGAs;
constructing a synchronization graph having a plurality of edges which correspond to communication paths of the netlist from respective originating sequential cells to respective destination sequential cells;
in at least one case where a subset of the communication paths being communicated between the first and second FPGAs exceeds a number of physical connections between the first and second FPGAs on the electronic board:
determining travel times of each of the subset of the communication paths for respective signals by combining:
a first intra-FPGA travel time corresponding to time required to perform one or more logical operations within the first FPGA on the respective signal;
an inter-FPGA travel time for an inter-chip portion of the each communication path between the first FPGA to the second FPGA;
and
a second intra-FPGA travel time corresponding to time required to perform one or more logical operations within the second FPGA on the respective signal;
integrating one or more serializers and one or more deserializers into the first and second FPGAs to multiplex selected ones of the subset of communication paths, wherein one or more of the selected communication paths have lower travel time and higher degree of multiplexing than one or more non-selected communication paths of the subset of communication paths;
and
configuring the electronic board to implement the ASIC netlist and the integrated serializer(s) and deserializer(s).

8 more elements

A system for developing a multi-FPGA prototype of an application-specific integrated circuit (ASIC), wherein the multi-FPGA prototype is implemented on an electronic board having a plurality of FPGA-type programmable chips (FPGAs) including a first FPGA and a second FPGA, the system comprising:

one or more computers configured to:
segment a netlist of the ASIC according to a number of the plurality FPGAs;
construct a synchronization graph having a plurality of edges which correspond to communication paths of the netlist from respective originating sequential cells to respective destination sequential cells;
in at least one case where a subset of the communication paths being communicated between the first and second FPGAs exceeds a number of physical connections between the first and second FPGAs on the electronic board:
determine travel times of each of the subset of the communication paths for respective signals by combining:
a first intra-FPGA travel time corresponding to time required to perform one or more logical operations within the first FPGA on the respective signal;
an inter-FPGA travel time for an inter-chip portion of the each communication path between the first FPGA to the second FPGA;
and
a second intra-FPGA travel time corresponding to time required to perform one or more logical operations within the second FPGA on the respective signal;
integrate one or more serializers and one or more deserializers into the first and second FPGAs to multiplex selected ones of the subset of communication paths, wherein one or more of the selected communication paths have a lower travel time and a higher degree of multiplexing than one or more non-selected communication paths of the subset of communication paths;
and
configure the electronic board to implement the ASIC netlist and the integrated serializer(s) and deserializer(s).

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/907,501Filed 8 Jul 2014
Priority: FR 13 5741626 Jul 2013
Published: US 2016/0161551 A19 Jun 2016
Granted: 6 Nov 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

G01R 31/2882
Testing of integrated circuits [IC]: testing timing characteristics
G01R 31/2834
Specific tests of electronic circuits not provided for elsewhere: automated test systems [ATE]; using microprocessors or computers
G01R 31/31725
Testing of digital circuits: timing aspects, e.g. clock distribution, skew, propagation delay
G06F 30/331
Using simulation: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Family

US 2016/0161551 A1Pre-grant publication · published 9 Jun 2016
US 10,120,019 B2This patent

From the US filing history. Foreign family members aren’t listed.

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