Adaptive thermal actuator array for wafer-level applications
AssigneeIntel Corporation
InventorEric J. M. Moret
Life of this patent
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Abstract
Embodiments of the present disclosure describe wafer-level die testing devices having a base with a planar X-Y surface, a plurality of thermal actuators situated on the surface, wherein one or more of the plurality of thermal actuators is movable in relation to the base in at least one of the X or the Y directions, and one or more adjustable links, wherein each adjustable link is to adjust a relative position between an individual thermal actuator of the plurality of thermal actuators and one or more other thermal actuators of the plurality of thermal actuators in one or more of the X or the Y directions. Other embodiments may be described and/or claimed.
Claims25
A wafer-level die testing apparatus comprising:
- a base having a planar X-Y surface in an X-Y-Z Cartesian coordinate system;
- a plurality of thermal actuators situated on the surface, wherein one or more of the plurality of thermal actuators is movable in relation to the base in at least one of the X or the Y directions;
- and
- one or more adjustable links, wherein each adjustable link is operable to adjust a relative position between an individual thermal actuator of the plurality of thermal actuators and one or more other thermal actuators of the plurality of thermal actuators in one or more of the X or the Y directions.
A wafer-level die testing apparatus comprising:
- a base having a planar X-Y surface in an X-Y-Z Cartesian coordinate system;
- and
- a plurality of thermal actuators situated on the surface, wherein each thermal actuator in the plurality of thermal actuators includes:
- an independently controllable temperature control mechanism;
- a thermal surface;
- and
- an independently controllable z-drive that adjusts a distance between the thermal surface and the planar surface of the base in the Z direction.
A method of wafer-level die testing comprising:
- positioning, in response to a controller, a wafer having a plurality of dies such that one die of the plurality of dies is adjacent to a thermal surface of a thermal actuator coupled with a base;
- setting, in response to the controller, the thermal actuator to a first temperature set point;
- performing, in response to the controller, cold defect testing at the first temperature set point;
- setting, in response to the controller, the thermal actuator to a second temperature set point above the first temperature set point;
- and
- performing, in response to the controller, functional testing of the die at the second temperature set point.
One or more computer-readable media comprising instructions that cause a controller coupled with a wafer-level die testing device, in response to execution of the instructions by the controller to:
- adjust at least one of a first pitch in a first direction, X, or a second pitch in a second direction, Y, normal to the X direction of a plurality of thermal actuators situated on a base of the wafer-level die testing device;
- dynamically control a first temperature of a first thermal actuator of the plurality of thermal actuators during wafer-level die testing;
- and
- dynamically control a second temperature of a second thermal actuator of the plurality of thermal actuators independently of the dynamic control of the first temperature.
Dependencies are inferred from the claim text.